Non-Hysteretic Condition in Negative Capacitance Junctionless FETs

Abstract

This paper analyzes the design space stability of negative capacitance double gate junctionless FETs (NCDG JLFET). Using analytical expressions derived from a charge-based model, we predict instability condition, hysteresis voltage, and critical thickness of the ferroelectric layers giving rise to the negative capacitance behavior. The impact of the technological parameters is investigated in order to ensure hysteresis-free operation. Finally, the stability of NCDG JLFET is predicted over a wide range of temperatures from 77 K to 400 K. This approach has been assessed with numerical TCAD simulations.