Non-Intrusive Persistence with a Backend NVM Controller

Abstract

Abstract-By providing instruction-grained access to vast amounts of persistent data with ordinary loads and stores, byte-addressable storage class memory (SCM) has the potential to revolutionize system architecture. We describe a non-intrusive SCM controller for achieving light-weight failure atomicity through back-end operations. Our solution avoids costly software intervention by decoupling isolation and concurrency-driven atomicity from failure atomicity and durability, and does not require changes to the front-end cache hierarchy. Two implementation alternatives -one using a hardware structure, and the other extending memory controller with a firmware managed volatile space, are described.

Hardware transactional persistent memory

“…e Persistent Memory Controller is shown in Figure 1. While super cially similar to an earlier design [18,19,23], this controller includes enhancements to handle the subtleties of using HTM rather than locking for concurrency control, and makes signi cant simplications by shi ing some of the responsibility for the maintenance of PM state to the recovery protocol.…”

“…e Persistent Memory Controller uses the dependency set concept from [18,19,23] to temporarily park any processor cache eviction in a searchable Volatile Delay Bu er (VDB) so that its e ective time to reach PM is no earlier than the time that the last possible transaction with which the eviction could have overlapped has become recoverable. e Persistent Memory Controller in this work improves upon the backend controller of [18] by dispensing with synchronous log replays and victim cache management. e library also covers any writes to PM variables by volatile write-aside log entries made within the speculative scope of an HTM transaction; and then streaming the transactional log record into a non-volatile PM area outside the HTM transaction.…”

“…Adding a small DRAM bu er in front of Persistent Memory to improve latency and to coalesce writes was proposed in [40]. e use of a volatile victim cache to prevent uncontrolled cache evictions from reaching PM was described in [17][18][19], but requires so ware locking for concurrency control. FIRM [42] describes techniques to di erentiate persistent and non-persistent memory tra c, and presents scheduling algorithms to maximize system throughput and fairness.…”

“…Low-level memory scheduling to improve e ciency of persistent memory access was studied in [41]. Except for [17][18][19], none of these works deal with the issues of atomicity or durability of write sequences. Our approach e ectively uses HTM for concurrency control and does not require changes to the font-end cache controller or use logs for replaying transactions to PM.…”

“…Existing PM programming frameworks separate into categories based on the degree of change they require in the processor architecture for such problems. Several works [9][10][11][12][13] operate with existing processor capabilities and write a log (either a write-ahead log or an undo log) durably to cover data changes arriving via the volatile cache hierarchy; some [14][15][16] require signi cant changes to existing cache hardware and protocols in the processor microarchitecture, while others [17][18][19] only require external controllers not a ecting the processor core.…”