Non-uniform yield optimization for integrated circuit layout

Pikus, Fedor G.; Torres, J. Andres

doi:10.1117/12.746722

Cited by 5 publications

(2 citation statements)

References 8 publications

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“…This means that empty areas or long stretches of metal do not have or need any correction applied. The composition result is a good indication of the nature of the apparent constant improvement that was obtained in previous investigations 1 . Since for all the processes the composition is mainly dominated by the unmodified layout, one could expect that the scores would be in absolute terms very close to each other when comparing the global absolute score.…”

Section: Resultssupporting

confidence: 56%

Non-uniform yield optimization for integrated circuit layout considering global interactions

Torres

Pikus

2008

Photomask Technology 2008

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In a previous work we have shown a yield optimization metric and a technique that considers the effects of several types of yield enhancement methods for a given layout. Those findings suggested that it is important to consider two types of yield tradeoffs, local tradeoffs where addressing one yield loss mechanism degrades others in the immediate vicinity of the correction (local optimization window), and global tradeoffs where the net effect of the correction can be fully accounted only when considering neighboring optimization windows. Such conclusion was derived from the fact that the locally optimized layouts did not completely realize the theoretically optimal yield, which was obtained from the assumption that global tradeoffs could be fully resolved. This work focuses in the contribution that such global tradeoffs have on the final yield score when accounted properly during the optimization.While the previous work focused only in selecting the corrections that locally improved the yield score 1 , this work evaluates the global interactions before and after a change, and the correction is only accepted if it improves the global score. While the global optimization requires a more expensive computational process, the intention of this work is to determine how close the optimal layout can be from its theoretical limit. Since the optimization is performed and evaluated under four different types of processes in which the failure mechanisms vary in relative importance, it is possible to derive conclusions as to the need of considering global effects when trading off runtime requirements with quality of the correction.

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Section: Resultssupporting

confidence: 56%

Non-uniform yield optimization for integrated circuit layout considering global interactions

Torres

Pikus

2008

Photomask Technology 2008

Self Cite

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“…For example, understanding the area impact, the loss of redundancy, the impact on electrical parameters drives the sort of design change that can be contained within the parameters of functionality, power and yield expected for a certain part [3]. In the two examples depicted by Figure 8, the demands of redundancy rules for the benefit of critical area improvement negatively impact the printability of the two constructs.…”

Section: Design Challengesmentioning

confidence: 98%

Methodology for balancing design and process tradeoffs for deep-subwavelength technologies

et al. 2011

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For process development of deep-subwavelength technologies, it has become accepted practice to use model-based simulation to predict systematic and parametric failures. Increasingly, these techniques are being used by designers to ensure layout manufacturability, as an alternative to, or complement to, restrictive design rules. The benefit of modelbased simulation tools in the design environment is that manufacturability problems are addressed in a design-aware way by making appropriate trade-offs, e.g., between overall chip density and manufacturing cost and yield.The paper shows how library elements and the full ASIC design flow benefit from eliminating hot spots and improving design robustness early in the design cycle. It demonstrates a path to yield optimization and first time right designs implemented in leading edge technologies. The approach described herein identifies those areas in the design that could benefit from being fixed early, leading to design updates and avoiding later design churn by careful selection of design sensitivities. This paper shows how to achieve this goal by using simulation tools incorporating various models from sparse to rigorously physical, pattern detection and pattern matching, checking and validating failure thresholds.The time when design rule (DR) correct layouts could be processed in the manufacturing lines with no or minimal post tape out intervention is long past. Many advanced techniques have been developed to improve the lithographic entitlement. Their success allowed for the design to concentrate on producing best manufacturable "target" design in the hope that the manufacturing can reproduce it on wafer, but things became more complicated as the critical dimension shrank further. To control the risk of systematic failure the tendency is to make the design rules more complex, but this in itself does not guarantee pattern fidelity. With fewer companies manufacturing integrated circuitry and with increasing technology complexity, designers have become more interested in using all the information available to improve design manufacturability. This and the well understood increased difficulty of capturing design intent leads to increased motivation for manufacturing, technology development, and design teams to collaborate to create high yield parts creating a "must fix" contract. Design and process co-optimization becomes the norm. This process encompasses the tool and tuning capability to determine critical constructs, identifying those with the worst performance, and the guidance to resolve those manufacturability issues. A margin for adverse variation is also accounted for within the performance consideration.The goal of this paper is to show that a consistent framework provides a mechanism to detect and rank manufacturability problems in design, while guiding the correction process. A predefined set of guidelines is needed to understand what degree of process knowledge is sufficient for building a useful DfM tool.

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