Nonblocking DRAM Refresh

Nguyen, Kate; Lyu, Kehan; Meng, Xianze; Sridharan, Vilas; Jian, Xun

doi:10.1109/mm.2019.2907486

Cited by 4 publications

(4 citation statements)

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“…As the number of cells increases in the DRAM memory, the requirement of longer or frequent refresh operations induced maximum stalls during execution. To mitigate this problem, Kate et al [72] proposed a non‐blocking DRAM refresh scheme where read access refreshes the data present in the memory block. Non‐blocking refresh can refresh a portion of the data present in the memory block and improves DRAM refresh overhead of all the DRAM‐based memories used in servers, personal computers, GPUs, embedded platforms, etc.…”

Section: Approaches To Efficient Memory Managementmentioning

confidence: 99%

Survey on memory management techniques in heterogeneous computing systems

Hazarika

Poddar

Rahaman

2020

IET Computers & Digital Techniques

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A major issue faced by data scientists today is how to scale up their processing infrastructure to meet the challenge of big data and high-performance computing (HPC) workloads. With today's HPC domain, it is required to connect multiple graphics processing units (GPUs) to accomplish large-scale parallel computing along with CPUs. Data movement between the processor and on-chip or off-chip memory creates a major bottleneck in overall system performance. The CPU/GPU processes all the data on a computer's memory and hence the speed of the data movement to/from memory and the size of the memory affect computer speed. During memory access by any processing element, the memory management unit (MMU) controls the data flow of the computer's main memory and impacts the system performance and power. Change in dynamic random access memory (DRAM) architecture, integration of memory-centric hardware accelerator in the heterogeneous system and Processing-in-Memory (PIM) are the techniques adopted from all the available shared resource management techniques to maximise the system throughput. This survey study presents an analysis of various DRAM designs and their performances. The authors also focus on the architecture, functionality, and performance of different hardware accelerators and PIM systems to reduce memory access time. Some insights and potential directions toward enhancements to existing techniques are also discussed. The requirement of fast, reconfigurable, self-adaptive memory management schemes in the high-speed processing scenario motivates us to track the trend. An effective MMU handles memory protection, cache control and bus arbitration associated with the processors.

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Section: Approaches To Efficient Memory Managementmentioning

confidence: 99%

Survey on memory management techniques in heterogeneous computing systems

Hazarika

Poddar

Rahaman

2020

IET Computers & Digital Techniques

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“…As the number of cores in modern multi‐core systems increases, the need for bigger and more efficient main memory becomes crucial. With shrinking technological sizes, it becomes simpler to construct greater main memory as memory density increases 1 . However, it becomes increasingly difficult to reduce the energy consumption and access latency of such large memory 1 .…”

Section: Introductionmentioning

confidence: 99%

“…With shrinking technological sizes, it becomes simpler to construct greater main memory as memory density increases 1 . However, it becomes increasingly difficult to reduce the energy consumption and access latency of such large memory 1 . Due to its improved density and capacity as well as its low production costs, DRAM has become the primary component of most contemporary main memories 2,3 .…”

Section: Introductionmentioning

confidence: 99%

“…Due to the recent increase in memory‐intensive applications, the DRAM is being increased to meet their requirements. Consequently, the energy required to retain the data in the DRAM cells via periodic refresh increases essentially with the size of the main memory 1 . Refresh activities in a DRAM are accountable for up to fifty percent of the DRAM's power consumption 4,5 .…”

Section: Introductionmentioning

confidence: 99%

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WinDRAM: Weak rows as in‐DRAM cache

Kumar

Sinha

Das

2022

Concurrency and Computation

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The primary factor responsible for increasing the refresh rate is the presence of weak rows in a DRAM. They have a shorter retention time and lose charge faster than regular rows. Recently, a technique known as in-DRAM cache was introduced in which some DRAM rows act as a separate module. The in-DRAM cache can be used for a variety of purposes in DRAM. We present WinDRAM, an in-DRAM cache comprised of all the DRAM's weak rows. The most recently accessed rows are copied into the in-DRAM cache so that when the row is accessed again, both rows (original and copy) can be activated at the same time. Such simultaneous activation reduces activation time and, as a result, DRAM access latency. Dual-row activation is the term for this concept. Because weak rows are part of the in-DRAM cache and are frequently accessed, WinDRAM does not perform a periodic refresh on them. Existing techniques based on in-DRAM cache do not design the in-DRAM cache using weak rows. WinDRAM proposes a novel idea by designing the in-DRAM cache using weak rows. Because the weak rows do not need to be refreshed, the refresh interval of the remaining rows can be increased, resulting in a refresh rate reduction of 80% to 90%. The speedup is 15% to 25% faster than standard DRAM and 12.77% faster than previous work for high memory-intensive workloads. Overall energy consumption is also reduced by 10% to 15%. K E Y W O R D SDRAM refresh, dual-row activation, in-DRAM cache, weak row INTRODUCTIONModern, high-performance computers require both on-chip and off-chip memory designs that are efficient. As the number of cores in modern multi-core systems increases, the need for bigger and more efficient main memory becomes crucial. With shrinking technological sizes, it becomes simpler to construct greater main memory as memory density increases. 1 However, it becomes increasingly difficult to reduce the energy consumption and access latency of such large memory. 1 Due to its improved density and capacity as well as its low production costs, DRAM has become the primary component of most contemporary main memories. 2,3 Typically, a DRAM bank is partitioned into many subarrays, as described in Section 2.Each subarray stores several DRAM cells in a 2D fashion (having rows and columns). Each DRAM cell is responsible for storing a single bit of data.The capacitor included within the cell stores the bit as a charge. For instance, a completely charged capacitor indicates that the cell contains bit 1.However, DRAM cells are leaky and lose their charge over a period of time (retention time). To keep the data contained within these cells, periodic refresh procedures must be done. Due to the recent increase in memory-intensive applications, the DRAM is being increased to meet their requirements. Consequently, the energy required to retain the data in the DRAM cells via periodic refresh increases essentially with the size of the main memory. 1 Refresh activities in a DRAM are accountable for up to fifty percent of the DRAM's power consumption. 4,5 In addition, these opera...

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