Nonlinear viscoelastic dilation of SiO2 films

Rafferty, C. S.; Landsberger, L. M.; Dutton, R.W.; Tiller, W. A.

doi:10.1063/1.101440

Cited by 28 publications

(14 citation statements)

References 16 publications

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“…These values are consistent with the typical data collected among previous studies related to dry oxides [18], [19]. Table II summarizes the value of each aforementioned empirical parameter incorporated into the current model versus the temperature of oxidation.…”

Section: ) Calibration Of the Low-stress Viscositysupporting

confidence: 76%

“…It should be pointed out that the resulting stress-dependent viscosity drop, as expressed in (3), is very closed to the Eyring's model [18], where the plasticity threshold is set to 0.66 10 dyn/cm for 1000 C, and 0.88 10 dyn/cm for 1100 C. Thus, the above values for were also fixed. Finally, in order to accurately determine the third empirical parameter, namely, the low-stress viscosity , a long dry oxidation has been performed on various silicon pillar shapes at both 1000 C and 1100 C, leading to sufficient oxide growth to set the proper value.…”

Section: Calibration and Experimental Validation Of The Modelmentioning

confidence: 99%

“…Hence, the motivation of this paper is to propose an analytical tool to accurately predict, with reasonable computing time, the sharpening of silicon pillars induced by their stress-dependent oxidation. This model is based on the well-known Deal and Grove one-dimensional oxidation law [14] and takes into account the effect of the local curved silicon surface and the stress-dependent physical parameters according to the theory developed by Kao et al [15], [16] and Rafferty and Dutton [17] and Rafferty et al [18]. This paper reports both the complete modeling of the oxidation sharpening mechanism and an experimental validation performed for several initial silicon pillar shapes at 1000 C and 1100 C under dry oxidation conditions.…”

Section: Introductionmentioning

confidence: 99%

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Modeling and Experimental Validation of Sharpening Mechanism Based on Thermal Oxidation for Fabrication of Ultra-Sharp Silicon Nanotips

Agache¹,

Ringot²,

Bigotte³

et al. 2005

IEEE Trans. Nanotechnology

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This paper aims at modeling the thermal oxidation of silicon pillars leading to the formation of very sharp silicon tips. The model is used to determine optimum process parameters with respect to the initial shape of the silicon pillars and the geometry of the desired tip. The modeling concept is to extend a previous approach, which predicts the oxidation mechanism of silicon cylinders versus their initial radius. The silicon pillar geometry is approximated by a superposition of silicon cylindrical structures featuring a local curvature radius. Experimental validation has been performed for several initial silicon pillar shapes, at 1000 C and 1100 C under dry oxidation conditions, leading to formation of very sharp silicon tips. The numerical predictions are shown to agree well with these experimental data. The motivation of this study aims at designing and fabricating a nanoelectromechanical filter device. Its vibrating part consists of a silicon nanotip, covered with a thin gold layer, the geometrical features of which affect the center frequency of the nanofilter device.

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Section: ) Calibration Of the Low-stress Viscositysupporting

confidence: 76%

Section: Calibration and Experimental Validation Of The Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Modeling and Experimental Validation of Sharpening Mechanism Based on Thermal Oxidation for Fabrication of Ultra-Sharp Silicon Nanotips

Agache¹,

Ringot²,

Bigotte³

et al. 2005

IEEE Trans. Nanotechnology

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“…25,26 In our experimental case ͑dry oxidation at 900°C for some hours͒ we have evaluated by a simple calculation the time for viscous flow to develop, that is, the time for the stress to reach the steady-state value. 29 This time is, by using a linear model and viscosity values measured by Fargeix and Ghibaudo, 30 of about 50 min, i.e., smaller than the whole oxidation duration ͑some hours͒. As a consequence, we have assumed in our model a deformation of SiO 2 by viscous flow.…”

Section: Modeling Of the Si Nanocrystal Oxidationmentioning

confidence: 99%

Oxidation of Si nanocrystals fabricated by ultralow-energy ion implantation in thin SiO2 layers

Coffin

Bonafos

Schamm

et al. 2006

Journal of Applied Physics

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Articles you may be interested inModeling stress retarded self-limiting oxidation of suspended silicon nanowires for the development of silicon nanowire-based nanodevices Journal of Applied Physics 110, 033524 (2011) The effect of thermal treatments in nitrogen-diluted oxygen on the structural characteristics of two-dimensional arrays of Si nanocrystals ͑NCs͒ fabricated by ultralow-energy ion implantation ͑1 keV͒ in thin silicon dioxide layers is reported. The NC characteristics ͑size, density, and coverage͒ have been measured by spatially resolved electron-energy-loss spectroscopy by using the spectrum-imaging mode of a scanning transmission electron microscope. Their evolution has been studied as a function of thermal treatment duration at a temperature ͑900°C͒ below the SiO 2 viscoelastic point. An extended spherical Deal-Grove ͓J. Appl. Phys. 36, 3770 ͑1965͔͒ model for self-limiting oxidation of embedded silicon NCs has been carried out. It proposes that the stress effects, due to oxide deformation, slow down the NC oxidation rate and lead to a self-limiting oxide growth. The model predictions show a good agreement with the experimental results. Soft oxidation appears to be a powerful way for manipulating the NC size distribution and surface density.

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“…The thermal oxide in SOLES Structure C is grown at lower temperature and is therefore of higher quality, with lower OH incorporation 18 and higher density. 19,20 Ge diffusivity in Structure C is indeed an order of magnitude lower than that in Structure B.…”

mentioning

confidence: 95%

Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

Pacella

Bulsara

Drazek

et al. 2015

ECS J. Solid State Sci. Technol.

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The Silicon on Lattice Engineered Substrate (SOLES) platform enables monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal oxide semiconductor (CMOS) devices. The SOLES wafer provides a device quality Si-on-Insulator (SOI) layer for CMOS device fabrication and an embedded III-V device template layer which serves as a seed surface for epitaxial growth of III-V devices. In this work, different approaches for fabricating SOLES wafers comprised of Ge and InP template layers are characterized and InP-based SOLES structures are demonstrated for the first time. Ge-based SOLES are robust for long durations at temperatures up to 915 • C and Ge diffusion can be controlled by engineering the oxide isolation layers adjacent to the Ge. InP SOLES structures alleviate lattice and thermal expansion mismatches between the template layer and subsequent device layers. Although allowable processing temperatures for these wafers had been expected to be higher due to the higher melting temperature of InP, high indium diffusion through the SiO 2 and InP melting actually lead to lower thermal stability. This research elucidates approaches to enhance the process flexibility and wafer integrity of Ge-based and InP-based SOLES. Monolithic integration of III-V compound semiconductor (III-V) and silicon (Si) complementary metal-oxide semiconductor (CMOS) enables advanced circuits with increased performance and functionality and promotes system-level miniaturization. The Silicon on Lattice Engineered Substrate (SOLES) platform is a Si wafer with embedded III-V template layer that has been developed for III-V/Si integration and is illustrated in Fig. 1. 1,2 A silicon-on-insulator (SOI) layer on top provides the high quality substrate necessary for CMOS device processing whereas the III-V template acts as a seed layer for epitaxial III-V device growth. This III-V template layer is accessed by etching windows through the top Si and buried insulator layers. The SOLES substrate structure is designed to add functionality to a CMOS platform while maintaining compatibility with Si processing infrastructure. Exposure to the III-V template layer is avoided until the CMOS process sequence is complete and the III-V device epitaxy and processing can be treated in a similar manner to backend metal processing.

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Nonlinear viscoelastic dilation of SiO2 films

Cited by 28 publications

References 16 publications

Modeling and Experimental Validation of Sharpening Mechanism Based on Thermal Oxidation for Fabrication of Ultra-Sharp Silicon Nanotips

Modeling and Experimental Validation of Sharpening Mechanism Based on Thermal Oxidation for Fabrication of Ultra-Sharp Silicon Nanotips

Oxidation of Si nanocrystals fabricated by ultralow-energy ion implantation in thin SiO2 layers

Fabrication and Thermal Budget Considerations of Advanced Ge and InP SOLES Substrates

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