Proceedings of the Workshop on Memory Systems Performance and Correctness 2014
DOI: 10.1145/2618128.2618136
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Nonvolatile memory is a broken time machine

Abstract: Energy harvesting enables intermittently powered devices to compute without built-in power. But frequent power failures, combined with nonvolatile memory intended to protect computational state, introduce strange control flow that turns sequential code into unwieldy concurrent code: programs must grapple with their own state from previous interrupted runs. This paper describes the broken time machine problem for these devices and outlines potential solutions from the perspective of safe concurrent programming.

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Cited by 74 publications
(57 citation statements)
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“…Some of the more recent systems requiring hardware support to checkpoint include [3,4,7,33,48], Table 1 summarizes the data that get copied to and from the non-volatile memory in service of memory consistency and progress preservation. Checkpointing volatile state alone does not ensure data consistency when the system can directly manipulate non-volatile memory [56]. Precisely, data can get inconsistent when code includes a write-after-read (WAR) dependency between operations that manipulate non-volatile memory.…”
Section: Intermittent Executionmentioning
confidence: 99%
“…Some of the more recent systems requiring hardware support to checkpoint include [3,4,7,33,48], Table 1 summarizes the data that get copied to and from the non-volatile memory in service of memory consistency and progress preservation. Checkpointing volatile state alone does not ensure data consistency when the system can directly manipulate non-volatile memory [56]. Precisely, data can get inconsistent when code includes a write-after-read (WAR) dependency between operations that manipulate non-volatile memory.…”
Section: Intermittent Executionmentioning
confidence: 99%
“…Because power failures are frequent, they can occur while a (non-volatile) data structure is being modified. When the platform reboots, the program will restart with inconsistent data, causing the socalled broken time machine problem [9]. A possible solution would be to have the processor itself non-volatile [10].…”
Section: B Nvram For Transiently-powered Systemsmentioning
confidence: 99%
“…[45] have explored the possibility of concurrent programming under intermittent energy and the various efforts required to maintain program consistency. These issues are addressed by means of atomic instructions allied with an on-chip capacitance to ensure that the processor has sufficient power to complete the ongoing instruction.…”
Section: B Architectural Aspects Of Energy Harvestingmentioning
confidence: 99%