NORM: An FPGA-based Non-volatile Memory Emulation Framework for Intermittent Computing

Abstract

Today’s intermittent computing systems operate by relying only on harvested energy accumulated in their tiny energy reservoirs, typically capacitors. An intermittent device dies due to a power failure when there is no energy in its capacitor and boots again when the harvested energy is sufficient to power its hardware components. Power failures prevent the forward progress of computation due to the frequent loss of computational state. To remedy this problem, intermittent computing systems comprise built-in fast non-volatile memories with high write endurance to store information that persists despite frequent power failures. However, the lack of design tools makes fast-prototyping these systems difficult. Even though FPGAs are common platforms for fast prototyping and behavioral verification of continuously-powered architectures, they do not target prototyping intermittent computing systems. This article introduces a new FPGA-based framework, named NORM ( N on-volatile mem OR y e M ulator), to emulate and verify the behavior of any intermittent computing system that exploits fast non-volatile memories. Our evaluation showed that NORM can be used to emulate and validate FeRAM-based transiently-powered hardware architectures successfully.

Intermittent-Aware Design Exploration of Systolic Array Using Various Non-Volatile Memory: A Comparative Study

“…As previously explained, each PE is equipped with two registers (one volatile and one non-volatile). To mimic the function of non-volatile registers, we adopted the method proposed in the NORM architecture [ 20 ]. We implemented a signal that interconnects all components, excluding non-volatile registers.…”

“…Architecture-level techniques for intermittent computing offer various solutions to overcome the challenges of power failures and optimize energy efficiency [ 19 , 20 ]. Approximate computing techniques are used to reduce the accuracy of computations for improved performance and efficiency.…”

Intermittent Computing Emulation of Ultralow-Power Processors: Evaluation of Backup Strategies for RISC-V

“…To implement and evaluate our different backup policies and their performance, we have made use of the non-volatile simulation framework developed especially for intermittent computing applications on off-the-shelf FPGAs [18], [36] by integrating the RISC-V core. The framework consists of an Intermittency Emulator Module (IEMU) which gives informed predictions of a possible power failure, and a NV-memory module that helps emulate the behavior of a fast built-in NVmemory.…”

“…The next 16 memory locations after the 64 kB are reserved for non-volatile (NV) memory, or NV REG. For this, we have made use of a non-volatile simulation framework developed especially for intermittent computing applications on offthe-shelf FPGAs [18]. This FPGA-based framework, named NORM (Non-volatile memORy eMulator), is developed to emulate and verify the behavior of any intermittent computing system that exploits fast non-volatile memories.…”

“…Therefore, these strategies can be easily extended to a wide variety of different processors. To implement and evaluate our different backup policies, we used the non-volatile simulation framework developed especially for intermittent computing applications on off-the-shelf FPGAs [18]. We explore the effect of our backup strategies on the execution performance of intermittent programs on the Ibex RISC-V processor.…”