2014
DOI: 10.1049/iet-pel.2013.0652
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Normalised adaptive linear element‐based control of single‐phase self excited induction generator feeding fluctuating loads

Abstract: In this study, a new normalised adaline-based control algorithm is proposed to control voltage source converter (VSC) used for voltage control and harmonics mitigation of two-winding asymmetric single-phase self excited induction generator (SEIG) feeding fluctuating linear and non-linear loads. The proposed control algorithm is implemented on a digital signal processor (DSP). In the proposed SEIG system, a two-winding asymmetric single-phase SEIG is driven by a speed governor controlled diesel/biogas engine. T… Show more

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Cited by 51 publications
(25 citation statements)
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References 12 publications
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“…Another topology involves the use of a single-phase inverter bridge, with energy storage elements connected on its DC side [68][69][70]76] or without storage such in [77]. A more complex structure, named Decoupled Voltage and Frequency Controller (DVFC) [64,67], integrates both the inverter bridge and the ELC.…”
Section: (C)); •mentioning
confidence: 99%
“…Another topology involves the use of a single-phase inverter bridge, with energy storage elements connected on its DC side [68][69][70]76] or without storage such in [77]. A more complex structure, named Decoupled Voltage and Frequency Controller (DVFC) [64,67], integrates both the inverter bridge and the ELC.…”
Section: (C)); •mentioning
confidence: 99%
“…Block (12) is a zero-crossing detector, for which output e 4 is a square wave, as shown in Figures 2(b) and 2(c). e 4 is fed to amplifier block (14) and inverting amplifier block (13) in Figure 1(a). e 5 is k times e 4 and e 6 is -k times e 4 , and both signals are square wave.…”
Section: Control Schemementioning
confidence: 99%
“…e 7 (and e 5 ) is always complementary of e 8 (and e 6 ), as shown in Figure 2(d). The EMI filter removes the high-frequency EMI interference generated by the CMOSintegrated circuit of the inverting amplifier and amplifier, represented by blocks (13) and (14) in Figure 1(af). The outputs of blocks (15) and (16) (signals e 8 and e 7 ) are fed, respectively, to AND gate blocks (9) and (8) in Figure 1(a) as a third inputs.…”
Section: Control Schemementioning
confidence: 99%
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