Normalized Min-Sum Neural Network for LDPC Decoding

Wang, Qing; Liu, Qing; Wang, Shunfu; Chen, Leian; Fang, Haoyu; Chen, Luyong; Guo, Yanwen; Wu, Zhiqiang

doi:10.1109/tccn.2022.3212438

Cited by 14 publications

(11 citation statements)

References 34 publications

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“…Te decoding complexity can be signifcantly reduced thanks to various algorithms available for C2V messages m c i ⟶ v j updates simplifcation. Te widely used ones, in the recent works, are min-sum (MSA) and normalized min-sum (NMSA) algorithms [19][20][21]. For the MSA algorithm, the update equation became…”

Section: Llr Bp Decoding For Ldpc Codesmentioning

confidence: 99%

Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Benhayoun,

Razi,

Mansouri

et al. 2023

Applied Computational Intelligence and Soft Computing

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Ultra-reliable low-latency communications, URLLC, are designed for applications such as self-driving cars and telesurgery requiring a response in milliseconds and are very sensitive to transmission errors. To match the computational complexity of LDPC decoding algorithms to URLLC applications on IoT devices having very limited computational resources, this paper presents a new parallel and low-latency software implementation of the LDPC decoder. First, a decoding algorithm optimization and a compact data structure are proposed. Next, a parallel software implementation is performed on ARM multicore platforms in order to evaluate the latency of the proposed optimization. The synthesis results highlight a reduction in the memory size requirement by 50% and a three-time speedup in terms of processing time when compared to previous software decoder implementations. The reached decoding latency on the parallel processing platform is 150 μs for 288 bits with a bit error ratio of 3.410–9.

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Section: Llr Bp Decoding For Ldpc Codesmentioning

confidence: 99%

Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Benhayoun,

Razi,

Mansouri

et al. 2023

Applied Computational Intelligence and Soft Computing

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“…For example, in [17], the decoding performance of the LDPC decoder is improved by training additive offsets and weights. Alternatively, the approach presented in [18] focuses on training multiplicative correction factors for both the check node and variable node messages.…”

Section: Introductionmentioning

confidence: 99%

GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation

Hsu,

Liu,

Liao

et al. 2024

IEEE Open J. Circuits Syst.

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The trade-off between decoding performance and hardware costs has been a long-standing challenge in Low-Density Parity Check (LDPC) decoding. Based on model-driven methodology, the Neural Network-Aided Variable Weight Min-Sum (NN-aided vwMS) algorithm is proposed to address this dilemma in this paper. Not only eliminating the second minimum value in the check node update process for reducing hardware complexity, our approach featuring a fast-convergent shuffled scheduling method proposed to enhance convergence speed can also maintain similar decoding performance as compared to the traditional normalized min-sum algorithm. Different from existing model-driven methodologies only suitable for short codes, a Globally-Coupled Like (GC-like) LDPC code construction is presented to enable efficient training with simplified neural networks for longer LDPC codes. To demonstrate the capability of the NN-aided vwMS algorithm with the fast-convergent shuffled scheduling method, a GC-like (9126,8197) LDPC decoder is implemented for NAND flash applications, achieving a 6.56 Gbps throughput with a core area of 0.58 mm 2 under the 40-nm CMOS TSMC process, and average power consumption of 288 mW under the frame error rate of 2.64 × 10 −5 at 4.5dB. Compared to other works, our decoder architecture can accomplish a superior normalized throughput-to-area ratio of 11.31 Gbps/mm 2 , improving at least 2.4x on results in [1]-[4].

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“…The authors in [10] applied weight sharing to the decoding algorithm of long LDPC codes, optimized the parameters according to the degree of nodes, and proposed Neural 2-dimensional Normalized decoders. The authors in [11] used the weight sharing algorithm in the proposed NNMS decoding algorithm, and then quantized the parameters of the neural decoding network using the bit quantization algorithm. The authors in [5] proposed a parameter sharing mechanism for P-LDPC, which reduces the training complexity and storage cost.…”

Section: Introductionmentioning

confidence: 99%

Joint-Way Compression for LDPC Neural Decoding Algorithm With Tensor-Ring Decomposition

Liang

Lam

2023

IEEE Access

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In this paper, we propose low complexity joint-way compression algorithms with Tensor-Ring (TR) decomposition and weight sharing to further lower the storage and computational complexity requirements for low density parity check (LDPC) neural decoding. Compared with Tensor-Train (TT) decomposition, TR decomposition is more flexible for the selection of ranks, and is also conducive to the use of rank optimization algorithms. In particular, we use TR decomposition to decompose not only the weight parameter matrix of Neural Normalized Min-Sum (NNMS)+ algorithm [16], but also the message matrix transmitted between variable nodes and check nodes. Furthermore, we combine the TR decomposition and temporal and spatial weight sharing algorithm, called joint-way compression, to further lower the complexity of LDPC neural decoding algorithm. We show that the joint-way compression algorithm can achieve better compression efficiency than a single compression algorithm, while maintaining a comparable bit error rate (BER) performance. From the numerical experiments, we found that all the compression algorithms with appropriate selection of ranks give almost no performance BER degradation and that the TRwm-ssNNMS+ algorithm, which combines the spatial sharing and TR decomposition of both weight and message matrix, has the best compression performance. Comparing with our TT-NNMS+ algorithm proposed in [16], the number of parameters is reduced by about 70 times and the number of multiplications is reduced by about 6 times.

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Normalized Min-Sum Neural Network for LDPC Decoding

Cited by 14 publications

References 34 publications

Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation

Joint-Way Compression for LDPC Neural Decoding Algorithm With Tensor-Ring Decomposition

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