Novel 20nm hybrid SOI/bulk CMOS technology with 0.183μm/sup 2/ 6T-SRAM cell by immersion lithography

This paper describes an analytical MOSFET model for 20nm CMOS. The model includes the gate voltage dependence of the channel length modulation parameter. It is found that the channel length modulation parameter extracted from experimental data has remarkable gate voltage dependence in sub 65nm region. The dependence has been successfully modeled and included in an analytical MOSFET model. This model can predict the current -voltage characteristics with in good accuracy for n-channel and p-channel MOSFETs down to 20nm.

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Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate

Feng

Liu

Griffin

et al. 2006

IEEE Electron Device Lett.

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The monolithic integration of germanium-on-insulator (GeOI) p-MOSFETs with silicon n-MOSFETs on a silicon substrate is demonstrated. The GeOI p-MOSFETs are fabricated on the oxide for silicon device isolation based on the newly developed rapid-melt-growth method. CMOS inverters consisting of the silicon n-MOSFET and GeOI p-MOSFET were obtained, and the measured results show that the processing of high-performance GeOI devices is compatible with bulk-silicon technology.

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Novel 20nm hybrid SOI/bulk CMOS technology with 0.183μm/sup 2/ 6T-SRAM cell by immersion lithography

Cited by 12 publications

References 1 publication

Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices

Electrical Characteristic Fluctuations in Sub-45nm CMOS Devices

An analytical MOSFET model including gate voltage dependence of channel length modulation parameter for 20nm CMOS

Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate

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