Novel 3-D structure for ultra high density flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same PlanE)

ECS J. Solid State Sci. Technol.

Ahn

Qin

et al. 2014

In this study, the effects of pad temperature on the chemical mechanical polishing (CMP) of tungsten were investigated. During polishing, the pad temperature was monitored and the removal rate behavior with respect to the pad temperature evolution was explored. The pad temperature was increased during tungsten CMP, and the tungsten removal rate increased accordingly. Further, it was found that the two had a strong correlation. Although tetraethyl orthosilicate (TEOS) polishing experiment showed that the pad temperature increased similarly under various experimental conditions, the TEOS removal rate did not change for all conditions. A novel pad-cooling nozzle effectively reduced the pad temperature during tungsten polishing and influenced the tungsten removal rate drop. Table motor current monitoring revealed that friction forces were almost identical under all experimental conditions for tungsten polishing regardless of the application of pad cooling. On the basis of pad temperature and table motor current data, it was clear that the tungsten removal rate was determined by temperature, indicating that the tungsten removal mechanism was mostly driven by a chemical reaction. Further, the pad cooling function can be used to control the tungsten removal rate effectively, resulting in a stable tungsten CMP process.Chemical mechanical polishing (CMP) is one of the most critical processes for enabling sub-10 nm device manufacturing. The usage of the CMP process has rapidly increased owing to the increasing demands for planarized surfaces to be used in microprocessor manufacturing. Post-etch and deposition processes render a wafer surface uneven and bumpy; only the CMP process results in a globally flat wafer surface by chemical/electrochemical softening and removal of material by the mechanical action of slurry abrasive. In addition to its original role of planarization to meet the depth of focus (DOF) target for lithography, increasing demand for planarized surfaces for use as interconnects from middle end of the line (MEOL) to back end of the line (BEOL), 1 the fabrication of new three-dimensional stacked devices and emerging fin field-effect transistors (FinFET) requires a more challenging CMP process. 2-5 Moreover, recently developed high-k metal gate structures (HKMG) control the gate height by CMP instead of the conventionally used dry etching process to meet the performance demands for future IC devices. 6-9 Thus, different from the traditional planar structure device fabrication, CMP directly touches a gate module, which makes CMP as a valuable alternative to the classical polysilicon gate process. Extremely high levels of uniformity, planarity, and defect controls are required to achieve so-called dummy gate-open CMP and replacement metal gate CMP successfully. 2,10 Furthermore, through-silicon via (TSV) packaging and wafer-bonding technology requires a more stringent CMP process than traditional local/global planarization. 4,5 Moreover, with the introduction of new materials such as III-V and germanium for us...

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confidence: 99%

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confidence: 99%

Effects of Pad Temperature on the Chemical Mechanical Polishing of Tungsten

ECS J. Solid State Sci. Technol.

Ahn

Qin

et al. 2014

“…In order to achieve much higher-density Flash devices with alleviated scaling problems, 3D cell structures [16][17][18][19][20][21][22][23][24] and multi-level-cells (MLCs) [25,3,5,[26][27][28]9] are feasible pathways forward and are currently being developed in nearly all semiconductor memory corporations. MLC chips containing two or three memory bits in a single cell have already been adopted as a standard in consumer electronics.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we report a breakthrough to increase memory density in a cost-effective manner by wafer level 3D memory chip architecture, called SMOL (stackedmemory-devices-on-logic). The SMOL has been realized through an innovative 3D memory device of a vertical-stackedarray-transistor (VSAT) [22] and interconnection structure of planarized-integration-on-the-same-plane (PIPE) [20].…”

Section: Introductionmentioning

confidence: 99%

A stacked memory device on logic 3D technology for ultra-high-density data storage

Hong²,

et al. 2011

Nanotechnology

We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures.

ECS J. Solid State Sci. Technol.

“…In particular, the recent development of three-dimensional (3-D) stack devices requires many CMP processing steps. [1][2][3][4] A typical CMP tool is composed of several consumables such as a polishing pad, chemical slurry, and a diamond conditioner. Further, it should be noted that the CMP performance is sensitive to the characteristics of these consumables.…”

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confidence: 99%

Contact Behavior and Chemical Mechanical Polishing (CMP) Performance of Hole-Type Polishing Pad

Kim¹,

Choi²,

Hong³

et al. 2012

A polishing pad plays an essential role in determining the chemical mechanical planarization (CMP) performance such as removal rate, planarization, and defectivity. Further, it is important for the polishing pad to maintain good CMP performance throughout its lifespan. In order to achieve high performance and durability, a hole-type pad was suggested as an alternative to the conventionally used pore-type pad. In this study, the effect of the hole density on the CMP performance was examined for a hole-type pad. Surface characterization of the hole-type pad showed that the hole density corresponded to the contact ratio between the pad and the wafer, and therefore, the contact characteristics could be controlled by a hole fabrication process. The experimental results showed that the number of holes play a key role in determining CMP performances. The removal rate decreased with an increase in the hole density. The level of dishing showed an increase with the hole density. The number of CMP scratches decreased at higher hole densities. Higher contact ratio and the presence of large particle trap sites explain the lower trend of the micro-scratch observed. An important advantage of the hole-type pad is that it retains the surface structure as CMP continues, which implies contact behavior is maintained.