Novel adaptive keeper LBL technique for low power and high performance register files

Abstract

This paper develops a novel adaptive keeper local bit line (LBL) technique to achieve low power and high performance register files design. To avoid increasing the implementation hardware overhead, the proposed technique employs a clock-combined unit to generate the body voltage of keeper. We evaluate the effectiveness of the proposed technique in a two-cycle 64-entries×32b register file design for 8GHz operation in 1V, 32nm high-K Metal-Gate technology. HSPICE simulation results show that the delay time is reduced by 29% and the power consumption is reduced by 36.1%-46.2% depending on the number of reading ports, as compared to the tradition register files design. Moreover, the proposed technique shows good robustness to noise and process variations.

A low-leakage and NBTI-mitigated N-type domino logic

“…In register files, LBLs (local bit lines) are often implemented by using a high fan-in domino MUX, as shown in Ref. [26]. If RWLs (read word lines) are set to be all-0 before entering standby mode, the pull-down network is disconnected from the GND.…”