Novel architecture for inverse mix columns for AES using ancient Vedic Mathematics on FPGA

Huddar, Sushma R.; Rupanagudi, Sudhir Rao; Ravi, R.; Yadav, Shikha; Jain, Sanjay

doi:10.1109/icacci.2013.6637476

Cited by 13 publications

(6 citation statements)

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“…1. The major functional blocks constitute a mixer, an NCO and a filter chain [3]. Firstly, the received input signal is multiplied with the IF sine signal from the NCO.…”

Section: Architectural Block Diagram Of Digital Down Convertermentioning

confidence: 99%

“…The filter chain consists of three levels of filtering [3]. The first stage consists of a 35 tap FIR filter, followed by decimation by a factor of 4 (denoted as D4 in Fig.…”

Section: Design Of Filter Chainmentioning

confidence: 99%

“…With the advances in wireless technology, information can be transmitted through a distance of few meters (Ex: Television remote control) to thousands of kilometers (Ex: Radio communication). This would indeed come at the cost of onchip area, speed and power where a lot of research is being carried out to optimize the same [1], [2], [3].…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of an Efficient 4G Digital down Converter used in Wireless Receiver Systems

G¹,

Aswatha²

2015

IJCA

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A Digital Down Converter (DDC), which is basically used to convert an intermediate frequency (IF) signal to its baseband form, forms an integral part of wireless receivers. The major functional blocks of a DDC constitute a mixer, Numerically Controlled Oscillator (NCO) and an FIR filter chain. In this paper, an area efficient and high speed DDC has been designed and implemented. On comparison of the results with that of the existing methodology, the designed architecture achieves 44.8% area efficiency and 80.7% improvement in speed.

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“…1. The major functional blocks constitute a mixer, an NCO and a filter chain [3]. Firstly, the received input signal is multiplied with the IF sine signal from the NCO.…”

Section: Architectural Block Diagram Of Digital Down Convertermentioning

confidence: 99%

“…The filter chain consists of three levels of filtering [3]. The first stage consists of a 35 tap FIR filter, followed by decimation by a factor of 4 (denoted as D4 in Fig.…”

Section: Design Of Filter Chainmentioning

confidence: 99%

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Design and Implementation of an Efficient 4G Digital down Converter used in Wireless Receiver Systems

G¹,

Aswatha²

2015

IJCA

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“…The image reconstruction is the main constituent module of the ECT digital processing unit. The inner-product constitutes the kernel operation of the matrix multiplication of numerous image and signal processing algorithms [21,22] and cryptography [23]. It is the core operation of the matrix-vector multiplication (MVM) used in linear-back projection (LBP) and the Landweber image reconstruction algorithms of the electrical capacitance tomography system [24][25][26].…”

Section: Introductionmentioning

confidence: 99%

Model-Based Hardware-Software Codesign of ECT Digital Processing Unit

Allam

Deabes

2021

Modelling and Simulation in Engineering

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Image reconstruction algorithm and its controller constitute the main modules of the electrical capacitance tomography (ECT) system; in order to achieve the trade-off between the attainable performance and the flexibility of the image reconstruction and control design of the ECT system, hardware-software codesign of a digital processing unit (DPU) targeting FPGA system-on-chip (SoC) is presented. Design and implementation of software and hardware components of the ECT-DPU and their integration and verification based on the model-based design (MBD) paradigm are proposed. The inner-product of large vectors constitutes the core of the majority of these ECT image reconstruction algorithms. Full parallel implementation of large vector multiplication on FPGA consumes a huge number of resources and incurs long combinational path delay. The proposed MBD of the ECT-DPU tackles this problem by crafting a parametric segmented parallel inner-product architecture so as to work as the shared hardware core unit for the parallel matrix multiplication in the image reconstruction and control of the ECT system. This allowed the parameterized core unit to be configured at system-level to tackle large matrices with the segment length working as a design degree of freedom. It allows the trade-off between performance and resource usage and determines the level of computation parallelism. Using MBD with the proposed segmented architecture, the system design can be flexibly tailored to the designer specifications to fulfill the required performance while meeting the resources constraint. In the linear-back projection image reconstruction algorithm, the segmentation scheme has exhibited high resource saving of 43% and 71% for a small degradation in a frame rate of 3% and 14%, respectively.

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“…Numerous contributions have been made to aid the physically challenged through developing fast algorithms to commute and communicate. Researchers all around the world have contributed to this growth by either enhancing the algorithms [3], [4], [5] involved or by improvising the architecture concerned to the hardware [6], [7], [8]. One of the most recent contributions to the mankind is the introduction of 4G systems.…”

Section: Introductionmentioning

confidence: 99%