Novel Bi-UWB on-Chip Antenna for Wireless NoC

The increasing demand for network and high-performance devices requires large data throughputs with minimal loss or repetition. Network on chips (NoC) provides excellent connectivity among multiple on-chip communicating devices with minimal loss compared with old bus systems. The motivation is to improve the throughput of the NoC that integrated on multicores for communication among cores by reducing the communication latency. The design of the arbiter in the crossbars switch of an NoC’s router has a vital role in judging the system’s speed and performance. Low latency and high-speed switching are possible with high performance and good switching equipment at the network level. One of the significant components in NoC under SoC design is the arbiter, which governs the system’s performance. Proper arbitrations can avoid network or traffic congestions like livelock and buffer waiting. The proposed work in this paper is to design an efficient and high productive arbiter for multicore chips, especially SoCs and CMPs. The proposed arbiter is showing good improvement in the throughput at higher data rates; an average of more than 10% throughput improvement is noticed at higher flit injection rates independent of the VCs implemented. Further, the critical delays are reduced to 15.84% with greater throughputs.

show abstract

“…Figure 1 shows a job run of a typical applicationoriented MPSoC. Smart MPSoC contains integrated hardware [8].…”

Section: Introductionmentioning

confidence: 99%

Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures

Sridhar

Krishnaiah²

2022

Journal of Sensors

View full text Add to dashboard Cite

show abstract

“…Wireless Networks on-chip (WiNoCs) exploit, at the chip scale, the advantages of wireless communication, which offers the possibility of reducing the network topological constraints, of avoiding inter-router hops, and of reducing the latency [7][8][9]. Although the use of very high frequencies (e.g., in the THz range) allows one to reduce the size of the radiators [10,11], the on-chip integrability of miniaturized antennas still requires intensive technological research.…”

Section: Introductionmentioning

confidence: 99%

4 × 4 Integrated Switches Based on On-Chip Wireless Connection through Optical Phased Arrays

et al. 2023

View full text Add to dashboard Cite

Optical Wireless Networks on-Chip are an emerging technology recently proposed to improve the interconnection between different processing units in densely integrated computing architectures. In this work, we propose a 4 × 4 optical wireless switch (OWS) based on optical phased arrays (OPAs) for broadband reconfigurable on-chip communication. The OPA and OWS design criteria are reported. Moreover, the performances of the OWS are analyzed and optimized considering the electromagnetic propagation in on-chip multilayer structures, with different thicknesses of the cladding layer. The effect on the OWS behavior of a non-ideal distribution of the power in input to the OPA is also investigated by designing a 1 × 7 beam splitter, based on a single-stage multi-mode interference (MMI) device to be used as a single element of the OWS. Then, the MMI output signals are considered in input to the transmitting OPAs and the OWS performances are evaluated.

show abstract

“…The advancement in chip integration technologies has set high upper limits on the number of cores attached to a single processing chip [1]. Further, the user eagerness to have fast processing outputs is an urge in some domestic or security devices; integrating many cores into a single chip is common in present processor design and chip manufacturing.…”

mentioning

confidence: 99%

Communication Latency and Power Consumption Consequence in Multi-Core Architectures and Improvement Methods

Sridhar

Krishnaiah²

2023

IJEER

View full text Add to dashboard Cite

The present electronics world has a lot of dependency on processing devices in the current and future developments. Even non-electronic industries have much data to process and are indirectly dependent on processors. The larger the number of processors incorporated into the architecture, will lower the data handling and processing time; thus, efficiency improves. Hence multi-core processors have become a regular part of the design of processing elements in the electronic industry. The large number of processors incorporated into the system architecture results in difficulty in communicating among them without a deadlock or live lock. NoC is a promising solution for communicating among the on-chip processors, provided it is fast enough and consumes less energy. Further, the latency among the multi-core processors should be optimal to stand with the increasing data acquisition and processing in the new/developing operating systems and software. This paper addresses energy efficiency and latency reduction methods/techniques for Multi-core architectures.

show abstract

Novel Bi-UWB on-Chip Antenna for Wireless NoC

Cited by 4 publications

References 39 publications

Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures

Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures

4 × 4 Integrated Switches Based on On-Chip Wireless Connection through Optical Phased Arrays

Communication Latency and Power Consumption Consequence in Multi-Core Architectures and Improvement Methods

Contact Info

Product

Resources

About