Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Abstract

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems

“…This circuit is usually known as a carry-save adder. Based on these fundamental findings more recent work has been done: For example in [9] and [10] new FPGA implementations of arithmetic circuits using RNS have been developed. Moreover, various applications could be sped up using RNS.…”

“…Only in the case of logical operations, a binary data path is still faster than the ternary variant. The overall speedup S of a program under test with c i instructions of type i is determined by(9) where s i is the speedup of an instruction of this type:…”