Novel design of multiplier-less FFT processors

Design FFT Processor Based on FPGA

“…The ASIC implementation would be faster in terms of the maximum operating clock frequency but the design with FPGA offers a more cost effective solution having short design cycle and the desktop development capability with the speed which is adequate for our specific application. [5] This paper introduced butterfly element, address generation unit and controller. Finally, it shows that the FFT processor operational results can meet requirements.…”

Acceleration of Computation Speed for Wavefront Phase Recovery Using Programmable Logic

“…In particular, multipliers consume much silicon area of FPGA because they are implemented with adder trees. Various implementation proposals have been made to save area removing these multipliers (Zhou et al 2007, Chang & Jen, 1998, Guo, 2000and Chien et al, 2005. Instead, DSP48 circuits allow some internal calculations of the Fourier transform algorithm or the filter of the phase reconstruction to be parallel, such as in complex multiplications.…”

A novel approach for DFT computation

“…This new algorithm also reduces the computational complexity by reducing the number of real additions and multiplications operation for the computation of DFT [8]. Zhou et al in 2007 proposed an FFT processor in such a manner that there is no multiplier unit in this process which reduces computational complexity and the designed structure solely depends on the number of additions operation involved in the computation. The multiplier operation usually requires more time than the execution of addition operation.…”

“…The multiplier operation usually requires more time than the execution of addition operation. Due to this, a lot of saving in execution time is expected by adopting this design approach [9].…”