2017
DOI: 10.1109/tpel.2016.2634009
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Novel Eliminated Common-Mode Voltage PWM Sequences and an Online Algorithm to Reduce Current Ripple for a Three-Level Inverter

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Cited by 33 publications
(12 citation statements)
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“…The four-leg inverter in [54] requires 8 power devices and an LC filter. Furthermore, the 3-level four-leg inverter in [57] requires 24 power devices and an LC filter, which makes its hardware cost far more than the traditional four-leg inverter [57] and 3-level inverters composed of 12 power switches and 6 diodes [59], [61], [63]. The paralleled inverters [65], [69] have the same amount of power switches as the 3-level inverters have, but the coupling inductors also contribute to the hardware cost of paralleled inverters.…”
Section: Comparison On Hardware Cost and Control Complexity Of Different Methodsmentioning
confidence: 99%
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“…The four-leg inverter in [54] requires 8 power devices and an LC filter. Furthermore, the 3-level four-leg inverter in [57] requires 24 power devices and an LC filter, which makes its hardware cost far more than the traditional four-leg inverter [57] and 3-level inverters composed of 12 power switches and 6 diodes [59], [61], [63]. The paralleled inverters [65], [69] have the same amount of power switches as the 3-level inverters have, but the coupling inductors also contribute to the hardware cost of paralleled inverters.…”
Section: Comparison On Hardware Cost and Control Complexity Of Different Methodsmentioning
confidence: 99%
“…To reduce the switching loss, a three-segment switching sequences for zero CMV modulation is realized in [60]. To reduce the current ripple and THD, a four-state ZCMV PWM is presented in [61] with its four PWM sequences. According to synthesizing reference vectors with different space vectors, three types of ZCMV PWM for three-level inverters are listed and comparatively studied in [62].…”
Section: Complex Topologies Of Inverter and Machinesmentioning
confidence: 99%
“…To sum up, how to reduce the switching loss and amplitude of common mode voltage is a problem that must be considered in the high power motor system. At present, domestic and overseas scholars have carried out extensive and in-depth research on the problems of high switching loss [6][7][8][9][10] and high common mode voltage [11][12][13][14][15] of multilevel inverters, and have made a series of achievements. In terms of switching loss reduction, in Reference [6], a closed-loop control strategy based on carrier modulation is proposed, in which the clamping region is inserted in every half fundamental period to reduce switching loss.…”
Section: Introductionmentioning
confidence: 99%
“…Additionally, the design and selection rules of the optimal switch sequence are obtained through the analysis of the current ripple. Based on the analysis of Reference [13], Reference [14] proposes a double zero vector synthesis sequence method, which can reduce the output current ripple while ensuring the zero common mode voltage amplitude of the inverter. In Reference [15], a method of reducing switching loss by adjusting the position of the zero vector in the sampling period is proposed, and the basic vector synthesis switching sequence with small common mode voltage amplitude is selected.…”
Section: Introductionmentioning
confidence: 99%
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