Novel high- K with low specific on-resistance high voltage lateral double-diffused MOSFET

Abstract

A novel voltage-withstand substrate with high-K (HK, k > 3.9, k is the relative permittivity) dielectric and low specific on-resistance (R on,sp ) bulk-silicon, high-voltage LDMOS (HKLR LDMOS)is proposed in this paper. The high-K dielectric and highly doped interface N + -layer are made in bulk silicon to reduce the surface field drift region. The high-K dielectric can fully assist in depleting the drift region to increase the drift doping concentration (N d ) and reshape the electric field distribution. The highly doped N + -layer under the high-K dielectric acts as a low resistance path to reduce the R on,sp . The new device with the high breakdown voltage (BV ), the low R on,sp , and the excellent figure of merit (FOM = BV 2 /R on,sp ) is obtained. The BV of HKLR LDMOS is 534 V, R on,sp is 70.6 mΩ•cm 2 , and FOM is 4.039 MW•cm −2 .

Modeling of high permittivity insulator structure with interface charge by charge compensation

“…Today, the power metal-oxide-semiconductor field-effect transistor (MOSFET) with high permittivity insulator structure (HKMOS) as a prospective power semiconductor switching has excellent advantages for applications in the low and medium power field. [1][2][3][4] The high permittivity (HK) pillar introduced into power MOSFET has no problem of charge imbalance potentially and replaces the superjunction (SJ), thereby optimizing the trade-off between specific ONresistance (R on,sp ) and breakdown voltage (BV) of power MOSFETs. [5,6] However, the existence of interface charge at the hetero-interface between HK pillar and silicon pillar is unavoidable, resulting in pre-avalanche breakdown.…”