A low noise 0.9 GHz FBAR clock consisting of an oscillator and divider circuit for single-sided-todifferential conversion for a high-speed interleaved pipeline A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 µm CMOS process, and tested. The circuit showed very good jitter and phase noise performance. A temperature coefficient of -47 ppm/K was measured.