Novel integration of ultrathin Al₂O₃ with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via

Abstract

Through-silicon-via (TSV) used in three-dimensional (3D) stacked dies must present small electrical parasitic, such as capacitance, to allow for low latency signal transmission. Stable TSV capacitance is desired to overcome the spatial circuit performance variation caused by non-uniform hot-spot heating. In this work, a novel combination of low-k with ultrathin Al2O3 bilayer liner is successfully integrated in the TSV. The TSV capacitance is reduced by ∼26% as compared to plasma-enhanced tetrahydrothosilicate (PETEOS) oxide liner. Stable TSV capacitance within the operating voltage of interest (∼0–5 V) is achieved by operating the TSV in a stable accumulation capacitance region. The positive shift in the flat-band voltage (ΔV FB = +19 V) is achieved by utilizing Al2O3-induced negative fixed charge (|Q f| = 1.3 × 1012 cm−2) at the Si/low-k interface. Leakage current density of the bilayer liner is improved to a level comparable with the PETEOS oxide liner post annealing [forming gas (N2/H2) at 350 °C for 2 h or 400 °C for 0.5 h]. Low-k material with a smaller elastic modulus improves the thermo-mechanical stress exerted on the surrounding Si substrate compared with PETEOS oxide.