Novel Interleaver Design for Turbo Codes

Pasricha, Shivani; Sharma, Sanjeev

doi:10.1007/s11277-015-2954-5

Cited by 3 publications

(3 citation statements)

References 32 publications

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“…In [19], a parallel interleaver structure with multiple on-the-fly computation of addresses has been proposed and a new scheduling scheme proposed to eliminate memory contention by efficient buffers, also analysis of maximum spread, largest spread QPP interleavers has been presented. A variant of QPP interleaver has been proposed in [20], which uses logical operators, multiplication and division operators to generate interleaving addresses in recursive manner based on algebraic analysis of QPP interleaver. This work proposes a new recursive computation of QPP formula for simplified reconfigurable QPP interleaver design for 3GPP LTE standard turbo channel coding system has been described.…”

Section: N Giri Prasadmentioning

confidence: 99%

Simplified on-The-Fly IAG QPP Interleaver for Turbo Channel Coding Scheme

Sujatha*¹,

Subhas²,

Prasad³

2019

IJRTE

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Interleaver is an indispensable component in the design of Turbo encoder and Turbo Decoder. QPP interleaver is a 3GPP specified conflict free interleaver for turbo channel coding scheme for all code block sizes of 40 to 6144. Thus the efficient design of a conflict free reconfigurable QPP interleaver for turbo encoder and turbo decoder is a pre-eminent task in turbo channel coding scheme. In this article, Design of a simplified reconfigurable (40 to 6144 block sizes) Recursive QPP interleaver for computation of address locations to minimize the computational complexity and to avoid storage of interleaver tables has been presented. The proposed interleaver will be further integrated in the design and implementation of high throughput parallel turbo decoder. The proposed design is synthesized and implemented using 28nm CMOS technology Zynq Zed FPGA and achieved low processing timing constraints, utilization and power constraints compared with other conventional designs.

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Section: N Giri Prasadmentioning

confidence: 99%

Simplified on-The-Fly IAG QPP Interleaver for Turbo Channel Coding Scheme

Sujatha*¹,

Subhas²,

Prasad³

2019

IJRTE

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“…The first decoding module consists of SISO decoding of convolutional codes and zigzag codes followed by only zigzag codes. Max* operator is used in SISO decoder to reduce the decoding complexity of the code . Equation defines Max* as

{max}^{*} ((), m, n) = max ((), m, n) + italicln ((), 1 + e^{(- |n - m|)})

and approximated as max*(m, n) ≈ max(m, n) for Max‐Log‐MAP algorithm.…”

Section: Modified Turbo Codesmentioning

confidence: 99%

“…Max* operator is used in SISO decoder to reduce the decoding complexity of the code. 18,19 Equation (6) defines Max* as…”

Section: Ofmentioning

confidence: 99%

A Novel Architecture of Modified Turbo Codes with an area efficient high speed interleaver

Ilango¹,

Chokkalingam²

2018

Concurrency and Computation

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Summary Modified Turbo Codes (MTC) is preferred over conventional Turbo Convolutional Codes (TCC) as they provide nearly the same performance but with the additional benefit of reduced decoding complexity. The Improved Low Complexity Hybrid Turbo Codes (ILCHTC) is a type of MTC, which achieves a Bit Error Rate (BER) performance near to Shannon's limit. This paper presents a high speed novel encoder structure called Enhanced ILCHTC and a high speed low power novel interleaver for the MTC and analyzes its BER performance. From the simulation results, it is observed that BER performance of Enhanced ILCHTC and ILCHTC with proposed interleaver is better and has high degree of error convergence and requires less than 50% of computations than TCC. From the synthesized results, it is observed that the computation time required to shuffle the bits by the proposed interleaver is 7.4% less than the time required by the existing interleaver. In addition, it is observed that the number of logic elements utilized by the proposed interleaver is 95, which is 8% less than the number of logic elements, utilized by the existing interleaver but the tradeoff is power, which is 1.63% more when compared to the existing interleaver. Thus, a high speed area efficient interleaver is proposed along with a novel encoder structure.

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Interleaver with high dimensional encoding principle using hybrid group search optimizer

Deshmukh

Panat

2017

2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)

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Novel Interleaver Design for Turbo Codes

Cited by 3 publications

References 32 publications

Simplified on-The-Fly IAG QPP Interleaver for Turbo Channel Coding Scheme

Simplified on-The-Fly IAG QPP Interleaver for Turbo Channel Coding Scheme

A Novel Architecture of Modified Turbo Codes with an area efficient high speed interleaver

Interleaver with high dimensional encoding principle using hybrid group search optimizer

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