Novel LDMOS with assisted deplete-substrate layer consist of super junction under the drain

Yuan, Shuai; Duan, Baoxing; Cai, Hai; Cao, Zhen; Yang, Yintang

doi:10.23919/ispsd.2017.7988951

Cited by 12 publications

(6 citation statements)

References 15 publications

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“…Since it can modulate both the lateral and vertical electric field, a more uniform electric field distribution can be obtained. In this way, the saturated BV of LDMOS has been broken by the deep drain region [19]. Although the Si/SiC LDMOS can obtain a higher BV, its R on,sp is slightly larger than the Si counterpart.…”

Section: Resultsmentioning

confidence: 99%

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

Duan

Xing

Yang

2019

Micro & Nano Letters

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A novel silicon (Si) on silicon carbide (SiC) lateral double-diffused metal oxide semiconductor field effect transistor with deep drain region is proposed. Its main idea is transferring the breakdown point and utilising the high critical electric field of SiC material to suppress the curvature effect of the drain, which eventually alleviates the trade-off relationship between breakdown voltage (BV) and specific on-resistance (R on,sp). Through the TCAD simulation, the results show that the BV is significantly improved from 240 V for conventional Si lateral double-diffused metal oxide semiconductor (LDMOS) to 384 V for the proposed structure with the drift region length of 20 μm, increased by 60%. The figureof-merit of the conventional Si LDMOS and the Si/SiC LDMOS are 2.04 and 4.26 MW/cm 2 , respectively. It indicates that the proposed structure has better performance than the Si counterpart. The influences of design parameters and interfacial charges on the device performance are also discussed in this work.

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Section: Resultsmentioning

confidence: 99%

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

Duan

Xing

Yang

2019

Micro & Nano Letters

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“…As shown in Figure 3, the higher the doping concentration of the pillars, the more sensitive the device blocking voltage to the charge imbalance. This is because the net imbalance charge in the highly doped pillars is much higher than the charge in lower-doped pillars, and the remained high-density carriers in the high-doped drift region significantly affects the electric file distribution, which leads to a remarkable breakdown voltage decrease [35][36][37]. The snapback phenomenon poses a significant adverse effect on RC-IGBTs, as the sudden voltage snapback with an increasing current leads to negative resistance in IGBTs.…”

Section: Breakdown Characteristicsmentioning

confidence: 99%

“…Only when both the N and P pillars are f rectangular electric field distribution be achieved in the drift region to blocking capability. As shown in Figure 3, the higher the doping conc lars, the more sensitive the device blocking voltage to the charge im cause the net imbalance charge in the highly doped pillars is much hig in lower-doped pillars, and the remained high-density carriers in th region significantly affects the electric file distribution, which leads to down voltage decrease [35][36][37]. The snapback phenomenon poses a significant adverse effect o sudden voltage snapback with an increasing current leads to negative However, the negative resistance characteristic is limited the paral snapback phenomena must be eliminated in RC-IGBTs.…”

Section: Breakdown Characteristicsmentioning

confidence: 99%

Analysis of the Operation Mechanism of Superjunction in RC-IGBT and a Novel Snapback-Free Partial Schottky Collector Superjunction RC-IGBT

Yuan,

Li,

Hou

et al. 2023

Micromachines

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This paper explores the operation mechanism of the superjunction structure in RC-IGBTs based on carrier distribution and analyzes the advantages and challenges associated with its application in RC-IGBTs for the first time. A Partial Schottky Collector Superjunction Reverse Conduction IGBT (PSC-SJ-RC-IGBT) is proposed to address these issues. The new structure eliminates the snapback phenomenon. Furthermore, by leveraging the unipolar conduction of the Schottky diode and its fast turn-off characteristics, the proposed device significantly reduces the turn-off power consumption and reverse recovery charge. With medium pillar doping concentration, the turn-off loss of the PSC-SJ-RC-IGBT decreases by 54.1% compared to conventional superjunction RC-IGBT, while the reverse recovery charge is reduced by 52.6%.

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“…LDMOS. The electric field distribution of the proposed device is optimized uniform and smooth, since it can modulate the vertical and lateral electric field through the deep drain region and SIPOS field plate [13,29]. So high BV can be obtained by increasing LD.…”

Section: Regionmentioning

confidence: 99%

Novel Si/SiC Heterojunction Lateral Double-Diffused Metal Oxide Semiconductor With SIPOS Field Plate by Simulation Study

Duan

Xue

Huang

et al. 2021

IEEE J. Electron Devices Soc.

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A novel Si/SiC heterojunction Lateral Doublediffused Metal Oxide Semiconductor with the Semi-Insulating Polycrystalline Silicon field plate (SIPOS Si/SiC LDMOS) is proposed in this paper for the first time. The innovative terminal technology of Breakdown Point Transfer (BPT) had been applied on Si/SiC MOSFETs. This creative technology improved Breakdown Voltage (BV) of the proposed device, compared with the conventional Si LDMOS (Cov. LDMOS). In order to optimize the trade-off between BV and Specific On-Resistance (RON,SP), the SIPOS field plate is applied on Si/SiC LDMOS for the first time in this paper. At On-State, due to the internal electric field of SIPOS filed plate, the majority carriers accumulation layer is formed on the surface of the drift region for the proposed SIPOS Si/SiC LDMOS, which means RON,SP will be reduced. Meanwhile, the electric field modulation effect of SIPOS field plate can make the surface electric field distribute evenly, which leads to an increase of BV. In addition, due to the high-thermal conductivity of SiC substrate, the heat-dissipation efficiency of the proposed device is significantly improved. The simulation results show that the BV of SIPOS Si/SiC LDMOS is 428.4V, which increased by 78.4% in comparison with Cov. LDMOS (BV of 240.0V) with the same structure parameters. The RON,SP of SIPOS Si/SiC LDMOS is decreased from 33.2mΩ•cm 2 of Cov. LDMOS to 24.0mΩ•cm 2 , decreased by 27.7%. Furthermore, the figure-of-merit (FOM=BV 2 /Ron,sp) of SIPOS Si/SiC LDMOS reaches 7.6MW/cm 2 , which means SIPOS Si/SiC LDMOS has enough performance to break the Silicon limit.

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Novel LDMOS with assisted deplete-substrate layer consist of super junction under the drain

Cited by 12 publications

References 15 publications

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

Si/SiC heterojunction lateral double‐diffused metal oxide semiconductor field effect transistor with breakdown point transfer (BPT) terminal technology

Analysis of the Operation Mechanism of Superjunction in RC-IGBT and a Novel Snapback-Free Partial Schottky Collector Superjunction RC-IGBT

Novel Si/SiC Heterojunction Lateral Double-Diffused Metal Oxide Semiconductor With SIPOS Field Plate by Simulation Study

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