Novel low-power 1-bit full adder design

Chen, Chuen-Yau; Chou, Yung-Pei

doi:10.1109/iscit.2009.5341063

Cited by 8 publications

(7 citation statements)

References 7 publications

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“…Because of small area of transistors used and low transistor count, the proposed full adder would save silicon area for other circuits. *The full adders were prototyped and simulated using TSMC 0.18µm technology with HSPICE at supply voltage of 1.8V and input signal frequency of 200 MHz These figures correspond to pre layout simulation [7]. **Evaluated at input signal frequency of 500MHz.…”

Section: Resultsmentioning

confidence: 99%

“…The performance parameters of other full adders have been quoted from reference [7]. It can be seen that the proposed adder offers considerably better performance in terms of both the speed and power consumption.…”

Section: Comparison With Other Full Adder Circuitsmentioning

confidence: 99%

“…Many other [5,6] proposed adder circuits suffer from the problem of degradation of logic levels at the outputs and poor driving capability. A full adder circuit based on multi-threshold CMOS (MTCMOS) technology with improved delay characteristics has also been reported [7].…”

Section: Introductionmentioning

confidence: 99%

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Low-Power High-Speed Small Area Hybrid CMOS Full Adder

Gupta¹,

Sharma²,

Dhavse³

2012

J Eng Technol

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A 20-transistor hybrid CMOS full adder circuit using small area transistors has been proposed. The circuit layout is designed with 0.18-µm n-well CMOS design rules. The post layout simulation has been carried out using TSMC018 technology file. The proposed adder circuit provides fully restored logic levels at the output for all input combinations up to an operating frequency of more than 500 MHz. The power dissipation, rise and fall times, and worst-case propagation delay as obtained from the proposed adder have been found to be better in comparison to other full adder circuits (which provide fully restored logic levels at the output) reported in the literature. ABSTRACTAccess this article online Website: www.onlinejet.net

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Section: Resultsmentioning

confidence: 99%

Section: Comparison With Other Full Adder Circuitsmentioning

confidence: 99%

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Low-Power High-Speed Small Area Hybrid CMOS Full Adder

Gupta¹,

Sharma²,

Dhavse³

2012

J Eng Technol

View full text Add to dashboard Cite

show abstract

“…The full adder is divided into two subcircuits. One is the circuit for SUM operation [9], and the other is the circuit for CARRYOUT operation. A.…”

Section: Basic Circuits For Constructing Multipliermentioning

confidence: 99%

“…3 shows the schematic of the CARRYOUT circuit. The core of this circuit is the domino logic that implements the function of CARRYOUT [9]. This circuit will stay in standby phase when the clock signal CLK is "logic 1".…”

Section: Basic Circuits For Constructing Multipliermentioning

confidence: 99%