Novel low‐power and stable memory cell design using hybrid CMOS and MTJ

Abstract

Memory is an essential component of any VLSI data storage system. Because of the shrinking of CMOS processing nodes, power consumption in conventional memory (SRAM and DRAM) increases. Traditional memory technologies also suffer several additional difficulties, such as limited scalability, low reliability, short data retention time, low durability, increased space, and latency, among others. As a result, new device technologies are critical for developing low-power, high-performance memory devices. Among the numerous developing nonvolatile (NV) memory technologies available today, STT-MRAM is regarded as one of the most appealing and promising NV memory technologies for overcoming the limitations of traditional memories. STT-MRAM is more efficient, quicker, NV, highly scalable, and readily integrated with CMOS technology. Because of the scalability of technology nodes below 45 nm, traditional STT-MRAM cells have several difficulties, including high write power consumption, destructive read and write operation, prolonged write time, and so on. To address the issues associated with the writing operation of STT-MRAM cells, this article presented an optimum STT-MRAM cell design based on PMA-MTJ. The write failure mitigation strategies are utilized to increase the proposed cell's write stability. A comparative analysis between conventional STT-MRAM cell and the proposed cell is performed by concerning the write power consumption, write delay, and write stability. The experimental results indicate the performance superiority of the proposed cell architecture.IP (in-plane), MTJ (magnetic tunnel junction), PMA (perpendicular magnetic anisotropy), STT-MRAM, write margin, write power | INTRODUCTIONSemiconductor memory devices and technologies, such as memory storage, are critical for data storage in electronics. Memory currently occupies more than 80% of the die area. This percentage is constantly increasing due to the continued reduction of the CMOS technology node below the 90-nm domain. Memory performance rises in terms of size and speed owing to technological scaling, while the static power consumption of CMOS-based memories increases due to an exponential growth in standby current. 1 Memory reliability is also impacted. The length of global interconnects

Low-Power Single Bitline Load Sense Amplifier for DRAM

“…Though other types of DRAM show advantages over 1T1C cell in read and write operations, the mostly used 1T1C cell has the smallest cell area, showing the best memory density compared to other DRAM cells [8]. With the significant growth in modern computing systems, DRAM has become a power/performance/energy bottleneck in data-intensive applications [9][10][11]. Power consumption is a major issue in low-power and portable devices.…”