Novel Methodology to Validate DUTs Using Single Access Structure

Pittala, Chandra Shaker; Sravana, J.; Ajitha, G.; Saritha, P; Khadir, Mohammad; Vijay, Vallabhuni; Venkateswarlu, S. China; Vallabhuni, Rajeev Ratna

doi:10.1109/iementech53263.2021.9614863

Cited by 12 publications

(10 citation statements)

References 23 publications

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“…We need to find out the Ci values. Signal Flow Graphs optimization techniques like retiming, pipelining and folding are not able to minimize the delay [4]. The integration of the filter which used the multiplied delay method and the masked filter is a complex optimization method which can't reduce the delay [1].…”

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confidence: 99%

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FPGA based Digital Filter Design for faster operations

2023

VLSI

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The reduced complexity design of the IIR filter is discussed in this paper. The use of the IIR filter has been variably increasing during the present times and they are realtime applications. The filter complexity reduction is done to increase the usage of filters in FPGA. In this method, the coefficients are expressed in the form of 1's and 0's. The multiplied delays have been used which is used to scale down the complexity. Signal Flow Graph plays a critical role in identifying the difficult path. IIR Filter is programmed on basis of the Synchronous Data Flow and Pipelining. The Half Band IIR filters are used for high-performance applications. This design is processed to implement in FPGA which will result in higher speed and the cost will be variably decreased as well as the consumption of power. The entire process is implemented by using the Verilog language which reduces the complication and speeds up the whole process.

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Section: Fig 3: Block Diagram For Masking Approachmentioning

confidence: 99%

“…In IIR filter, the output depends on past inputs, present inputs and previous outputs. [1][2][3][4][5][6][7][8][9][10][11][12][13][14] The transfer function can be written as…”

Section: Introductionmentioning

confidence: 99%

FPGA based Digital Filter Design for faster operations

2023

VLSI

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“…[3] The calculation of square root can be performed either by restoring or non-restoring using the digitby-digit technique. The methods proposed by Newton Rapshon and Goldschmidt [4] requires more hardware resources and has many steps involved than the digits by digits method. More hardware resources are necessary for restoring the approach.…”

Section: Introductionmentioning

confidence: 99%

Fundamental Digital Module Realization Using RTL Design for Quantum Mechanics

2023

VLSI

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Calculation of square root will be an essential mathematical operation that will have broad applications. In Hardware, the square root will be designed in order to gain power which will be quite low. Similarly, there are also other advantages that comes with gaining of low power that is high speed and also low area. A trade-off will also occur with the three metrics which is quite natural. As we know that the present technology is very advanced so it will aim for low power and architectural modification will be required by the relative designs. This sheet represents an energy efficient square rooter by using reversible logic. (RCSM) Reversible Controlled Subtract Multiplexer will be designing and it also plays an important part in implementing the binary square rooter. Saimur Rahman Gate will also be implementing the binary square rooter in order to improve and develop it. The Improvements such as cost of the quanta, inputs given by constants and also garbage outputs. The approaches such as conventional approach and SRG are used for designing the binary square rooter and it will be completed using non-restoring algorithm. Xilinx Software will be responsible for carrying out simulations and Synopsys Design Compiler will be the factor for obtaining power. The gate count which has been 75 will be decreased to 35. There will be an improvement of 20% in terms of power which will be obtained in this paper.

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“…[2] The combinational postponement is expanded due to the utilization of XOR & AND entryways. [29][30][31][32][33][34][35] By altering the ripple carry adder for improving region, CSLALOT is planned. [3] However, the speed of the engineering is decreased by the use of countless gatherings.…”

Section: Introductionmentioning

confidence: 99%

CSA Implementation Using Novel Methodology: RTL Development

2023

VLSI

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Carry Select Adder (CSLA) is an essentially utilized adder on account of its higher computational speed. CSLA is utilized in the space of incorporation frameworks. This paper proposes a CSLA design by carrying out the Logic Optimization Technique (ZFCLOT) using Zero Finding Logic contrasted with ordinary Zero Finding Logic (ZFC). This paper notices the different presentation measurements like area, power, delay, area delay product (ADP), power delay product (PDP) and effectiveness. Approval of the ZFCLOT put together CSLA is displayed with respect to Cadence stage utilizing 45 nm platform. The presented CSLA utilizing ZFCLOT has shown advanced execution measurements, explicitly, region and power improvement of 47.287% and 49.1%, separately contrasted with the current standard plans.

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Novel Methodology to Validate DUTs Using Single Access Structure

Cited by 12 publications

References 23 publications

FPGA based Digital Filter Design for faster operations

FPGA based Digital Filter Design for faster operations

Fundamental Digital Module Realization Using RTL Design for Quantum Mechanics

CSA Implementation Using Novel Methodology: RTL Development

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