Novel Multiple-Layer Stack Capacitor and Its Application in the IRPFA Readout Circuit

Liu, Qi; Wu, Tuanzhuang; Ma, Yue; Liu, Siyang; Xia, Xiaojuan; Sun, Weifeng

doi:10.1109/access.2021.3132490

Cited by 2 publications

(7 citation statements)

References 18 publications

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“…In terms of noise indicators, the small area array test results in this article have significant advantages compared to those in the literature (in 2016). In addition, the larger pixel array areas shown in references [14] (in 2021) and [15] (in 2023) are not on the same order of magnitude as the noise in this paper, but compared to the noise converted into a single pixel, this paper's findings are superior to those of [14] and similar to [15]. In terms of other indicators, as Refs.…”

Section: Discussionmentioning

confidence: 60%

“…The history of the development of infrared focal plane array detectors ranges from first-generation products, which mainly focused on scanning imaging with units and utilized multiple devices as cores [9], to the current fourth-generation system-level chip products [10]. At present, SUI, Attollo, Sony, and other companies have developed 5 µm center distance short wave infrared InGaAs focal plane detectors [11]; it can be seen that large-area arrays and high-performance readout circuits have become a trend [12][13][14][15]. Therefore, it is necessary to design a specialized infrared readout circuit to amplify and denoise the signal in order to ensure the effectiveness of signal extraction [16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

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The Design of a Low-Noise, High-Speed Readout-Integrated Circuit for Infrared Focal Plane Arrays

Mu,

Zhao,

Chen

et al. 2023

Sensors

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This paper describes the design of a low-noise, high-speed readout-integrated circuit for use in InGaAs infrared focal plane arrays, and analyzes the working principle and noise index of the pixel circuit in detail. The design fully considers the dynamic range, noise, and power consumption of the pixel circuit in which a capacitance transimpedance amplifier structure is adopted as the input stage circuit, and chip fabrication via an XFAB 0.18 µm CMOS process is successfully realized. The ROIC adopts monolithic integration and implements various functions, such as windowing, subsampling, and different integration and readout modes. The ROIC reached an array scale of 32 × 32, a frame rate of 100 Hz, and a readout rate of 20 Mbps with an analog power consumption of less than 52 mW. The measurement results show that the input reference noise can be reduced to 143 e- via the CDS, and the fully customized scheme has certain advantages in the research of high-performance ROICs.

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Section: Discussionmentioning

confidence: 60%

Section: Introductionmentioning

confidence: 99%

The Design of a Low-Noise, High-Speed Readout-Integrated Circuit for Infrared Focal Plane Arrays

Mu,

Zhao,

Chen

et al. 2023

Sensors

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“…This will be the case with any feasible initial IR detector chip misalignment (displacement). The rate of change of the decaying amplitude 𝑈 𝑚 , obtained using (11), can be also predicted. Figure 15 shows the chip motion decay magnitude for two scenarios assuming initial chip displacement of 3.0 and 4.5 m.…”

Section: Take Fig 14mentioning

confidence: 99%

“…There has been substantial research and development in IR detectors over the past 20 years, particularly in the context of their miniaturization, detector material developments (namely the use of compound semiconductors), and the design and fabrication of fine-pitch pixel arrays [5][6][7]. Current developments in IR detector and FPA technologies are driven by trends and demands for improved sensitivity and resolution of the imaging systems, continuing advances in sensing material compositions and their processing, and needs for high-yield low-cost fabrication capabilities [8][9][10][11]. For example, investigations by Teng et al focused on a novel metalorganic chemical vapor deposition method for growing infrared InAs/GaSb superlattice focal plane arrays [10], and Liu at al.…”

Section: Introductionmentioning

confidence: 99%

“…For example, investigations by Teng et al focused on a novel metalorganic chemical vapor deposition method for growing infrared InAs/GaSb superlattice focal plane arrays [10], and Liu at al. reported the successful implementation of an improved CMOS process with four-layer stack capacitor for the readout integrated circuit (ROIC) chip and demonstrated an FPA ROIC with improved dynamic range [11].…”

Section: Introductionmentioning

confidence: 99%

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Modeling Insights Into the Assembly Challenges of Focal Plane Arrays

Stoyanov

Bailey

2023

IEEE Access

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Ongoing technological advances in photodetector material growth and processing, readout integrated circuits, and robust hybridization (packaging) methods for assembling high-resolution and smallpitch size pixel arrays are the main enabling factors for pushing the frontiers of high-performance Focal Plane Array (FPA) technologies for imaging systems. This paper details the development of analytical and numerical models and demonstrates their use to generate insights into the feasibility of two flip-chip assembly processes for packaging infrared (IR) detector chips. The modelling studies focus on the challenges of forming the indium interconnection arrays in the case of the FPA technologies using Group III-V compound semiconductor materials and ultra-fine pitch pixel array layouts. The accurate alignment of the IR detector chip onto the readout chip in the case of high-density pixel architectures is a critical requirement for the packaging process. To gain better understanding of this requirement, which has a clear implication for the quality and subsequent reliability performance of the FPA, compression and reflow bonding process models are developed using suitable modeling approaches and methods and then demonstrated for two distinctive focal plane array design configurations. The novelty of this work is in the developed modeling capabilities utilizing different computational methods, from large deformation and contact analysis finite element to energy-based and harmonic motion mechanics, to characterize and optimize the mechanical and dynamic non-linear behavior of the indium solder joints and their formation during FPA packaging. The feasibility of bonding techniques for different resolution FPAs and under flip-chip misalignment conditions is assessed. The modeling results pointed to a very strict, sub-micrometer flip-chip placement accuracy requirement for the assembly of FPAs with ultra-fine indium bump array resolution.INDEX TERMS IR detectors, Focal Plane Array, compression bonding simulation, reflow self-alignment modeling, indium joints, ultra-fine pitch flip chip assembly, compound semiconductors.

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Novel Multiple-Layer Stack Capacitor and Its Application in the IRPFA Readout Circuit

Abstract: Date of publication xxxx 00, 0000, date of current version xxxx 00, 0000.

Cited by 2 publications

References 18 publications

The Design of a Low-Noise, High-Speed Readout-Integrated Circuit for Infrared Focal Plane Arrays

The Design of a Low-Noise, High-Speed Readout-Integrated Circuit for Infrared Focal Plane Arrays

Modeling Insights Into the Assembly Challenges of Focal Plane Arrays

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