Novel optimized implementations for the Piccolo cipher based on field‐programmable gate arrays

Abstract

In the era of the highly pervasive Internet of Things (IoT), the optimized implementation of lightweight cryptographic algorithms for protecting data security has extensively received attention, for instance, the Piccolo cipher. Piccolo is an ultra‐lightweight block cipher designed for extremely resource‐constrained devices. Currently, many optimized implementations of Piccolo have been proposed; however, these implementations are heavily rely on optimizing different architectures. Actually, these implementation schemes have all neglected the optimization of the core components. How to achieve the new optimized implementation of the Piccolo cipher (via both the architectures and the core components) appears to be an interesting problem. In this article, new circuit structures for components (key schedules and round functions) of the Piccolo are first proposed using fewer logic gates. Based on these circuit structures, three architectures (iterative, integrated iterative, and scalar) are proposed to maximize implementation performances. To demonstrate their effectiveness and practicality, these architectures are simulated and synthesized on different field‐programmable gate arrays (FPGA) devices. Compared with the existing architectures of Piccolo, the results indicate that the iterative architectures and the integrated iterative architecture provide a better trade‐off between area and throughput, and the scalar architectures provide the highest throughput. Especially for Piccolo‐128, the area of its iterative architecture is 30 look‐up tables (LUTs) and 22 slices less than the best known implementation; the throughput and efficiency are 68.56% higher and twice higher than the best known implementation, respectively. Compared with other block ciphers, the efficiency and area‐delay product of the Piccolo‐128 iterative architecture outperform PRESENT, GIFT, SIMON, Midori, SIMON, and SIMECK. Compared with the best results, its encryption efficiency has increased by 31.53%, and the area‐delay product has decreased by 44.63%.