Novel Process for Vertical Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) Fabrication

Masahara, Meishoku; Matsukawa, Takashi; Tanoue, H.; Ishii, Keisuke; Liu, Yongxun; Sakamoto, K.; Kanemaru, S.; Suzuki, Eiichi

doi:10.1143/jjap.42.4138

Cited by 6 publications

(3 citation statements)

References 8 publications

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“…Etching a via past the encapsulated structure is called self-aligned if the encapsulation is resistant to the process that is used to etch the overlying SiO 2 . [37][38][39] For example, self-aligned processing enables etching through an SiO 2 overlayer which simultaneously opens separate contacts landing on the source, drain and gate. While these processes improve packing density and relax lithography requirements, they impose severe selectivity requirements as multiple materials are landed on in one process.…”

Section: Pale Of Sio 2 In Ar/ C-c 4 F 8 Magnetically Enhanced Capmentioning

confidence: 99%

Plasma atomic layer etching using conventional plasma equipment

Agarwal

Kushner

2008

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

159

104

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The decrease in feature sizes in microelectronics fabrication will soon require plasma etching processes having atomic layer resolution. The basis of plasma atomic layer etching ͑PALE͒ is forming a layer of passivation that allows the underlying substrate material to be etched with lower activation energy than in the absence of the passivation. The subsequent removal of the passivation with carefully tailored activation energy then removes a single layer of the underlying material. If these goals are met, the process is self-limiting. A challenge of PALE is the high cost of specialized equipment and slow processing speed. In this work, results from a computational investigation of PALE will be discussed with the goal of demonstrating the potential of using conventional plasma etching equipment having acceptable processing speeds. Results will be discussed using inductively coupled and magnetically enhanced capacitively coupled plasmas in which nonsinusoidal waveforms are used to regulate ion energies to optimize the passivation and etch steps. This strategy may also enable the use of a single gas mixture, as opposed to changing gas mixtures between steps.

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Section: Pale Of Sio 2 In Ar/ C-c 4 F 8 Magnetically Enhanced Capmentioning

confidence: 99%

Plasma atomic layer etching using conventional plasma equipment

Agarwal

Kushner

2008

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

159

104

View full text Add to dashboard Cite

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“…Theoretical analysis 21,22) and three-dimensional simulation 23) have shown that the V th and S-slope strongly depend on the T si . Very recently, we have succeeded in the fabrication of the ideal rectangular-cross-section Si-fin channel FinFETs 19,20) and the vertical DG MOSFET with ultrathin Si walls [24][25][26] using the orientation-dependent wet etching technique. 27,28) However, very few studies 29,30) on the cross-sectional channel shape have been reported.…”

Section: Introductionmentioning

confidence: 99%

Cross-Sectional Channel Shape Dependence of Short-Channel Effects in Fin-Type Double-Gate Metal Oxide Semiconductor Field-Effect Transistors

Liu

Ishii

Masahara

et al. 2004

Jpn. J. Appl. Phys.

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The dependence of short-channel effects (SCEs) on the cross-sectional channel shape of the fin-type double-gate metal oxide semiconductor field-effect transistors (MOSFETs) has been experimentally investigated from the viewpoint of fin fabrication. The three types of fin-type double-gate MOSFETs (FinFETs) with a rectangular-cross-section channel on a (110)-oriented silicon-on-insulator (SOI) wafer, and a triangular and trapezoidal channels on a (100)-oriented SOI wafer were fabricated using the same orientation-dependent wet etching process. The experimental results show that the SCEs in rectangular-crosssection silicon (Si)-fin channel devices are well suppressed compared with those in a triangular or a trapezoidal Si-fin channel device fabricated using a similar mask pattern, in the regimes of the gate length of less than 85 nm and Si fin height of larger than 65 nm. The presented experimental results are valuable for FinFET design and fabrication.

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“…9,10,18) To remove surface damage and to improve the sidewall surface roughness of Si-fin channels, sacrificial oxidation and oxide-striping steps as well as hydrogen annealing should be performed. 10) On the contrary, we have recently succeeded in the fabricating damage-free FinFETs with an ideal rectangular cross-section Si-fin and a (111) channel surface, [12][13][14][15][16][17] and vertical DG MOSFETs with an ultrathin vertical Si wall [19][20][21][22][23][24] by orientation-dependent wet etching. 25,26) However, very few works 9,10) on eff in ordinary FinFETs have been reported.…”

Section: Introductionmentioning

confidence: 99%

Experimental Study of Effective Carrier Mobility of Multi-Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with (111) Channel Surface Fabricated by Orientation-Dependent Wet Etching

Liu

Sugimata

Ishii

et al. 2006

jjap

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We present an experimental study of effective carrier mobility ( eff ) of multi-fin-type double-gate metal-oxidesemiconductor field-effect transistors (FinFETs) with a (111) channel surface fabricated by orientation-dependent wet etching. The peak values of the obtained eff of electrons and holes are approximately 300 and 160 cm 2 /(V s), respectively, which are close to those in (111) bulk metal-oxide-semiconductor field-effect transistors (MOSFETs). Moreover, the effective electric field (E eff ) dependence of the eff of electrons and holes shows a good agreement with the mobility universal curves of (111) bulk MOSFETs. These results indicate that the quality and channel surface roughness of Si-fins by orientationdependent wet etching are excellent. The obtained results of eff are very useful for the modeling and design of FinFETcomplementary metal-oxide-semiconductor (CMOS) circuits and the developed wet etching technique is very attractive in the fabrication of ultrathin and high-quality Si-fin channels.

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Novel Process for Vertical Double-Gate (DG) Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) Fabrication

Cited by 6 publications

References 8 publications

Plasma atomic layer etching using conventional plasma equipment

Plasma atomic layer etching using conventional plasma equipment

Cross-Sectional Channel Shape Dependence of Short-Channel Effects in Fin-Type Double-Gate Metal Oxide Semiconductor Field-Effect Transistors

Experimental Study of Effective Carrier Mobility of Multi-Fin-Type Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with (111) Channel Surface Fabricated by Orientation-Dependent Wet Etching

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