Novel radiation-hardened latch design for space-radiation environments

Abstract

With the continuous progress of complementary metal-oxidesemiconductor (CMOS) technology, the size of memory is constantly reduced, which greatly increases the probability of the chip being interfered by radiation particles in the space environment. The traditional latch is no longer suitable for the space radiation environment. In this paper, a Radiation-hardened Polarity design Latch (RHPDL) circuit is proposed. The internal storage nodes of the cell are surrounded by full NMOS transistor or full PMOS transistor, which reduces the number of sensitive nodes and improves the circuit stability, making the circuit not only resistant to single node upset (SNU), but also resistant to double nodes upset (DNU). A fast data path is used between the input and output of the RHPDL cell to reduce the delay of data transmission.