Novel Realization of Quantum Ternary Mux and Demux

Khan, Asif Islam; Nusrat, N.; Khan, Salim; Hasan, Masud

doi:10.1109/icece.2006.355313

Cited by 3 publications

(1 citation statement)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The adder circuit is the most important arithmetic circuit used in almost all circuits, especially in algorithms such as Grover, Shor, and HHL algorithms. Binary adder circuits are proposed by references [73][74][75] and their ternary counterparts are given in references [76][77][78]. The adder circuit of reference [30] consists of 14 MS and shift gates and the circuit from reference [79] obtained using the genetic algorithm, has 13 MS and shift gates.…”

Section: Ternary Addermentioning

confidence: 99%

Ternary logic design in topological quantum computing

Ilyas¹,

Cui²,

Perkowski³

2022

J. Phys. A: Math. Theor.

View full text Add to dashboard Cite

A quantum computer can perform exponentially faster than its classical counterpart. It works on the principle of superposition. But due to the decoherence effect, the superposition of a quantum state gets destroyed by the interaction with the environment. It is a real challenge to completely isolate a quantum system to make it free of decoherence. This problem can be circumvented by the use of topological quantum phases of matter. These phases have quasiparticles excitations called anyons. The anyons are charge-flux composites and show exotic fractional statistics. When the order of exchange matters, then the anyons are called non-abelian anyons. Majorana fermions in topological superconductors and quasiparticles in some quantum Hall states are non-abelian anyons. Such topological phases of matter have a ground state degeneracy. The fusion of two or more non-abelian anyons can result in a superposition of several anyons. The topological quantum gates are implemented by braiding and fusion of the non-abelian anyons. The fault-tolerance is achieved through the topological degrees of freedom of anyons. Such degrees of freedom are non-local, hence inaccessible to the local perturbations. In this paper, the Hilbert space for a topological qubit is discussed. The Ising and Fibonacci anyonic models for binary gates are briefly given. Ternary logic gates are more compact than their binary counterparts and naturally arise in a type of anyonic model called the metaplectic anyons. The mathematical model, for the fusion and braiding matrices of metaplectic anyons, is the quantum deformation of the recoupling theory. We proposed that the existing quantum ternary arithmetic gates can be realized by braiding and topological charge measurement of the metaplectic anyons.

show abstract

Section: Ternary Addermentioning

confidence: 99%

Ternary logic design in topological quantum computing

Ilyas¹,

Cui²,

Perkowski³

2022

J. Phys. A: Math. Theor.

View full text Add to dashboard Cite

show abstract

High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits

et al. 2019

View full text Add to dashboard Cite

Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this paper proposes new ternary circuits aiming to lower the power delay product (PDP) to save battery consumption. The proposed designs include new ternary gates [standard ternary inverter (STI) and ternary nand (TNAND)] and combinational circuits [ternary decoder (TDecoder), ternary half-adder (THA), and ternary multiplier (TMUL)] using carbon nano-tube field-effect transistors (CNFETs). This paper employs the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate, and applying the dual supply voltages (V dd and V dd /2). The five proposed designs are compared with the latest 15 ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies; 180 simulations are performed to prove the efficiency of the proposed designs. The results show the advantage of the proposed designs in reduction over 43% in terms of transistors' count for the ternary decoder and over 88%, 99%, 98%, 86%, and 78% in energy consumption (PDP) for the STI, TNAND, TDecoder, THA, and TMUL, respectively. INDEX TERMS Carbon nano-tube field effect transistors (CNFET), ternary combinational circuits, ternary logic gates, multi-valued logic (MVL), power delay product.

show abstract