1999
DOI: 10.1109/68.740726
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Novel self-synchronization scheme for high-speed packet TDM networks

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Cited by 22 publications
(15 citation statements)
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“…It has been shown by combining switches based on nonlinear interference effects that more sophisticated all-optical logic functionalist can be realized. In particular, proof of concept has been given for optical address recognizers [13]- [15], optical bit-level synchronizers [16], [17], optical clock recovery circuits [18], optical shift registers with inverters [19], [20], optical memories with read-write abilities [21]- [24], binary half-and full adders [25], [26], pseudorandom number generators [27], optical parity checkers [28], and optical packet switches [29].…”
mentioning
confidence: 99%
“…It has been shown by combining switches based on nonlinear interference effects that more sophisticated all-optical logic functionalist can be realized. In particular, proof of concept has been given for optical address recognizers [13]- [15], optical bit-level synchronizers [16], [17], optical clock recovery circuits [18], optical shift registers with inverters [19], [20], optical memories with read-write abilities [21]- [24], binary half-and full adders [25], [26], pseudorandom number generators [27], optical parity checkers [28], and optical packet switches [29].…”
mentioning
confidence: 99%
“…0 Þ, which is correct in case of isotropic gain, whereas f can be estimated from the measured TE and TM amplification curves by using eqs. (4), (5), (15) and (16). In this case the polarisation dependent gain could be totally explained by the band filling effects that are represented by the factor f .…”
Section: Simulation Resultsmentioning
confidence: 98%
“…It has been shown by combining switches based on nonlinear interference effects, that more sophisticated all-optical logic functionalities can be realized. In particular, proof of concept has been given for optical address recognizers, [13][14][15] optical bit-level synchronizers, 16,17) optical clock recovery circuits, 18) optical shift registers with inverters, 19,20) optical memories with read-write abilities, [21][22][23][24] binary half-and full adders, 25,26) pseudorandom number generators, 27) optical parity checkers 28) and optical packet switches. 29) The processing speed of the digital optical logic based on resonant optical transitions as described above is restricted to approximately 200 GHz.…”
Section: Introductionmentioning
confidence: 99%
“…More recently, experiments have been reported where all the pulses of the packet share the same physical state [22], [23]. In these approaches, an SOA with a very long recovery time is required [22], which in turn introduces very long guard bands between the transmitted packets or specific coding techniques [23]. The packet-rate clock recovery proposed here only requires the clock recovery circuit described in the previous section and a single SOA to extract a single pulse from each incoming data packet without additional signaling or guard-band requirements.…”
Section: B Packet-rate Clock Recovery Circuitmentioning
confidence: 99%
“…More recently, experiments have been reported where all the pulses of the packet share the same physical state [22], [23]. In these approaches, an SOA with a very long recovery time is required [22], which in turn introduces very long guard bands between the transmitted packets or specific coding techniques [23].…”
Section: B Packet-rate Clock Recovery Circuitmentioning
confidence: 99%