Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications

Yamamoto, Y.; Makiyama, Hideki; Yamashita, T.; Oda, H.; Kamohara, S.; Sugii, Nobuyuki; Yamaguchi, Yasuo; Mizutani, Tomoko; Kobayashi, Masaharu; Hiramoto, Toshiro

doi:10.1109/vlsit.2015.7223665

Cited by 14 publications

(16 citation statements)

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“…Figure 10 shows cumulative plots of DRV before and after stress. Owing to the small variability of SOTB FETs, 18,19,[29][30][31][32] the worst DRV is less than 0.15 V. In multiple stress application, the DRV of the worst cell improves from 0.130 to 0.115 V. On the other hand, only a small improvement is obtained by single stress application.…”

Section: Resultsmentioning

confidence: 99%

“…A device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) silicon-on-thin-buriedoxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology 18,19) is used to demonstrate the above concept. The TEG is designed such that the terminals for a power supply (V DD ), a word line (WL), two bit lines (BLs), and two storage nodes (VL, VR) of each cell are directly accessible [Fig.…”

Section: Measurement Methodsmentioning

confidence: 99%

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Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

Mizutani¹,

Takeuchi²,

Saraya³

et al. 2018

Jpn. J. Appl. Phys.

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We propose a new version of the post fabrication static random access memory (SRAM) self-improvement technique, which utilizes multiple stress application. It is demonstrated that, using a device matrix array (DMA) test element group (TEG) with intrinsic channel fully depleted (FD) siliconon-thin-buried-oxide (SOTB) six-transistor (6T) SRAM cells fabricated by the 65 nm technology, the lowering of data retention voltage (DRV) is more effectively achieved than using the previously proposed single stress technique.

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Section: Resultsmentioning

confidence: 99%

Section: Measurement Methodsmentioning

confidence: 99%

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

Mizutani¹,

Takeuchi²,

Saraya³

et al. 2018

Jpn. J. Appl. Phys.

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“…An SRAM device matrix array test element group with FDSOI FETs fabricated by 65 nm technology 22,23) is used. Figure 1(a) shows a schematic of the SRAM cell.…”

Section: Min Measurementmentioning

confidence: 99%

Estimation of minimum operating voltage in fully depleted SOI SRAM cells using gamma distribution

Mizutani

Takeuchi

et al. 2022

Jpn. J. Appl. Phys.

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Minimum operating voltages (Vmin) of every cell on a 32kb fully-depleted (FD) SOI static random access memory (SRAM) macro are successfully measured. The competing Vmin distribution models, which include the gamma and log-normal distribution, are approximated using the generalized gamma distribution (GENG). It is found that Vmin of the cells follow the gamma distribution. This finding gives a simple method to estimate worst Vmin of an SRAM macro by measuring few samples and make linear extrapolation from the gamma distribution.

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“…These sensors will be integrated in smart cards and RFIDs, vehicular technologies, buildings, infrastructures, healthcare, smart energy, factories, and supply chain management [98][99][100], as well as on humans for improving regular day to day experience [101]. To achieve such functionalities and fulfill the futuristic vision, IoT devices will require: (i) increased intra-node processing for real-time decision making; (ii) robustness to environmental variations (reliability); (iii) ultra-low power operation; (iv) ultra-high density integrated NVM and (v) smart antennas for wireless communications [102][103][104][105][106] [100]. Furthermore, Hitachi researchers have studied how to profit from IoT for 10 years and used big data analysis to introduce the wearable happiness meter to unravel the link between physical motion and happiness [101].…”

Section: Introductionmentioning

confidence: 99%

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

2015

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Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

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Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications

Cited by 14 publications

References 0 publications

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

Lowering data retention voltage in static random access memory array by post fabrication self-improvement of cell stability by multiple stress application

Estimation of minimum operating voltage in fully depleted SOI SRAM cells using gamma distribution

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

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