Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints

Chen, Yuguang; Wen, Wan-Yu; Shi, Yiyu; Hon, Wing-Kai; Chang, Shih-Chieh

doi:10.1109/tcad.2014.2385759

Cited by 22 publications

(11 citation statements)

References 24 publications

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“…Compared with the integer programming (6), in constraint (8a) a new binary variable v (s,t) is introduced to indicate whether a unit flow (path) exists from source s ∈ V 1 to sink t ∈ V 2 . Besides, a new constraint (8b) is defined to ensure that there will be K paths from each source s ∈ V 1 to vertices in V 2 .…”

Section: Integer Linear Programming Formulationmentioning

confidence: 99%

“…Because there exist a large number of TSVs in a chip, these issues in turn lead to low chip yield. For example, [5], [6] reported a 60% chip yield for a chip with 20000 TSVs and only 20% yield for 55000 TSVs in IMEC process technology. Since yield and reliability is a primary concern in 3D ICs design, a robust fault-tolerance structure is imperative.…”

Section: Introductionmentioning

confidence: 99%

“…One key problem in TSV fault-tolerance design is the faulttolerance structure generation, where a number of functional TSVs and one or several spare TSVs are grouped together to provide redundancy. Chen et al [6] proposed a minimum spanning tree based method to group f-TSVs and form onefault-tolerance structures. However, the method is difficult to be applied to multiple-fault-tolerance structure generation.…”

Section: Introductionmentioning

confidence: 99%

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Adaptive 3D-IC TSV Fault Tolerance Structure Generation

Chen

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield and reliability is one of the key obstacles to adopt the TSV based 3D-ICs technology in industry. Various fault-tolerance structures using spare TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement, but a valid structure cannot always be found due to the lack of effective generation methods for fault-tolerance structures. In this paper, we focus on the problem of adaptive fault-tolerance structure generation. Given the relations between functional TSVs and spare TSVs, we first calculate the maximum number of tolerant faults in each TSV group. Then we propose an integer linear programming (ILP) based model to construct adaptive fault-tolerance structure with minimal multiplexer delay overhead and hardware cost. We further develop a speed-up technique through efficient min-cost-max-flow (MCMF) model. All the proposed methodologies are embedded in a top-down TSV planning framework to form functional TSV groups and generate adaptive faulttolerance structures. Experimental results show that, compared with state-of-the-art, the number of spare TSVs used for fault tolerance can be effectively reduced.Index Terms-3D-IC, fault-tolerance, TSV planning, TSV yield.

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Section: Integer Linear Programming Formulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Adaptive 3D-IC TSV Fault Tolerance Structure Generation

Chen

2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Therefore, the design of the RDL layer affects the signal integrity of the entire package. Plenty of work has been done to model and optimize the electrical performance of the conventional 3-D interconnects [40,41]. H. Wang et al [42] found that doubling the insulation layer between the isolated silicon substrate and the metal signal line in the RDL layer on the surface of the silicon transfer plate and decreasing the thickness of the CPW (co-planar waveguide) copper wire from 5 µm to 3 µm helped reduce the Signal Loss and Crosstalk.…”

Section: Silicon Interposer Structurementioning

confidence: 99%

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Tian

Liu

2018

Electronics

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Three-dimensional integrated circuits (3D IC) based on TSV (Through Silicon Via) technology is the latest packaging technology with the smallest size and quality. As a result, it can effectively reduce parasitic effects, improve work efficiency, reduce the power consumption of the chip, and so on. TSV-based silicon interposers have been applied in the ground environment. In order to meet the miniaturization, high performance and low-cost requirements of aerospace equipment, the adapter substrate is a better choice. However, the transfer substrate, as an important part of 3D integrated circuits, may accumulate charge due to heavy ion irradiation and further reduce the performance of the entire chip package in harsh space radiation environment or cause it to fail completely. Little research has been carried out until now. This article summarizes the research methods and conclusions of the research on silicon interposers and TSV technology in recent years, as well as the influence of high-energy heavy ions on semiconductor devices. Based on this, a series of research methods to study the effect of high-energy heavy ions on TSV and silicon adapter plates is proposed.Electronics 2018, 7, 112 2 of 29 wafer was invented by M.G Smith et al. [2], which opposite surfaces were connected ohmically to the degenerately doped portions to be electrically connected along the thru-connection. With further research and exploration, 2.5D/3D integration technology with TSV realized integrated circuits with advantages of high interconnection density, high performance, low power consumption, and low cost [3,4]. In addition, the core is widely considered to be the leading technology in the field of high density packaging in the future and is an effective way to break through Moore's Law [5][6][7]. Figure 1. Silicon interposer through electrical copper coating technology production: (a) The construction of through-silicon via on the wafer; (b) The dry film etchant is stuck on the wafer, then exposed and etched; (c) Hole plating and pad fabrication by electroplating methods; (d) The photoresist removing. Adapted with permission from [27], Copyright Elsevier, 2016.

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“…The TSVbased 3D stacking technology promises better performances, including smaller footprint, higher bandwidth, lower power and higher interconnect density. However, concerns about the 3D IC yield constitute one of the key obstacles for widespread industry adoption of 3D integration technology [1]. Defects in TSVs due to fabrication steps decrease the yield of 3D ICs, hence these defects need to be screened early in the manufacturing flow.…”

Section: Introductionmentioning

confidence: 99%

Vernier ring based pre-bond through silicon vias test in 3D ICs

Nie

Liang

et al. 2017

IEICE Electron. Express

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Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code.

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Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints

Cited by 22 publications

References 24 publications

Adaptive 3D-IC TSV Fault Tolerance Structure Generation

Adaptive 3D-IC TSV Fault Tolerance Structure Generation

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Vernier ring based pre-bond through silicon vias test in 3D ICs

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