Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology

Model for clipping‐induced timing error of bandwidth‐limited comparators

“…Introduction: A multitude of comparator applications depend upon the precisely timed crossing detection of the signal with the reference level, such as analogue-to-digital converters (ADCs), integrated pin electronics for automatic test equipment or time domain reflectometry. In the case of ADCs a timing mismatch between comparators of different reference levels as low as some per mil of the signal period may degrade the dynamic linearity of the ADC significantly [1], ultrasound pulse echo measurements require stable propagation delay even if the signal exhibits large amplitude variations [2,3] and limiting amplifiers for optical communication systems require the phase shift deviation to be small within widely different input signal powers [4]. Previous articles have addressed delay variations due to the input signal slew rate [2] and the bias dependence of the parasitic transistor capacitances [4].…”