Novel Ternary Logic Gates Design in Nanoelectronics

Low power CNTFET-based ternary multiplier for digital signal processing applications

“…Figure 8 depicts the timing diagram of efficient STI design, which is verified from table 2. STI circuits in [34] and [7] consume less power since two transistors are stacked, but the delay increases due to increase in transistors. The STIs are either working on single or dual power supply as tabulated in table 14.…”

“…CNTFETs are designed using one or multiple CNTs as channel whereas silicon is found in conventional Si-MOSFETs. CNTFETs use single-walled semiconducting CNT to achieve high driven current of 35 μA [7]. In contrast to Si-MOSFET technology, CNTFETs exhibit an effective gate capacitance, and each CNT demonstrates a current drive capability roughly 50% greater than Si-MOSFETs [8].…”

Low storage power and high noise margin ternary memory cells in nanoelectronics

“…This leads to the reduction of static power and also, noise margin improvement; however, there is also the problem of more transistor counts. In [21], a ternary memory cell has been designed by ternary latch using two cross‐coupled STIs with two supply voltages. Although these designs have been improved considerably in terms of the power dissipation and SNM, the use of two supply voltages is the main drawback of this design.…”

“…Many studies have been recently focused on the design of the multi‐valued logic in nanoelectronics using carbon nanotube field effect transistor (CNFET) such as multi‐digit ternary‐to‐binary converters [14–16], ternary full adder [17, 18], Multi‐valued Logic Comparator [19], ternary gates [20–23], Quaternary Full Adder [24, 25], ternary multipliers [26], ternary multi‐digit adders [27], ternary counter [28] and ternary memory cell [21, 29–32]. The basic architecture of static random access memory (SRAM) is organised as one or more rectangular arrays of memory cells with control circuitry.…”

“…The previous works are based on ternary latch based on cross coupled standard ternary inverter (STI) [21, 29–32, 35, 36]. The ternary latch based on STI has a low static noise margin (SNM) and a high storage power, as compared to a binary memory cell.…”