Numerical Analysis of Gate Stacks

Abstract

An efficient software tool for investigations on novel stacked gate dielectrics with emphasis on reliability has been developed. The accumulation, depletion, and inversion of carriers in MOS capacitors is properly considered for n-and p-substrates. The effect of carrier quantization on the electrostatics and the leakage current is included by treating carriers in quasi-bound states (QBS) and continuum states. The effect of interface traps and bulk traps in arbitrarily stacked gate dielectrics is taken into account. Trap assisted tunneling (TAT) is incorporated assuming an inelastic single step tunneling process. A brief overview of implemented models is given. The capabilities of our tool are demonstrated by several examples.