Numerical and experimental characterization of the thermal behavior of a packaged DRAM-on-logic stack

Oprins, Herman; Cherman, Vladimir; Vandevelde, Bart; Plas, G. Van der; Marchal, Paul Alfred; Beyne, Eric

doi:10.1109/ectc.2012.6248970

Cited by 24 publications

(13 citation statements)

References 20 publications

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“…3-b, which is temperature increase in the 3D circuit normalized with respect to the temperature increase in the single-die version (3D vs. 2D). The heat spreader behavior of non-thinned dies in a 3D stack was first introduced in [8] and is further discussed in the following section. Fig.…”

Section: A Thermal Test Circuitsmentioning

confidence: 99%

“…Thermal simulations are used in [4] and [5] to study the thermal effect of various design and technology parameters on 3D ICs subjected to hotspot heat sources. In addition to simulations, studies in [6][7] [8] report also experimental silicon data and expose some important aspects of the heat dissipation behavior in 3D ICs. There is, however, no thorough review of the thermal impact of the TSVbased 3D integration technology.…”

Section: Introductionmentioning

confidence: 99%

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Thermal performance of 3D ICs: Analysis and alternatives

Santos

Vivet

Colonna

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphitebased heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45ºC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.I.

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Section: A Thermal Test Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Thermal performance of 3D ICs: Analysis and alternatives

Santos

Vivet

Colonna

et al. 2014

2014 International 3D Systems Integration Conference (3DIC)

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“…A number of studies in literature examine specific thermal characteristics of die stacks. Oprins et al [3] investigated the thermal coupling between memory and logic dies in a two-tier stack in order to determine operating temperatures and thermal profiles in the memory. Their study used a thermal model calibrated with a 130nm stacked-die silicon test chip, and examined the influence of microbumps and underfill thermal conductivity on peak temperatures.…”

Section: Introductionmentioning

confidence: 99%

Physical characterization of steady-state temperature profiles in three-dimensional integrated circuits

Kumar

Zjajo

Leuken

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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The thermal performance of three-dimensional integrated circuits is influenced by a number of design and technology parameters. However, the relationship between these parameters and thermal behaviour of die stacks is complex and not well understood. In this paper, we perform a detailed evaluation of the influence of stack composition and depth, thickness of dies, physical location of power dissipating elements and stack power density on steady-state temperature profiles. We examine how each of these parameters affects heat spread within 3D ICs, and highlight the causes for hotspot formation. The results of our analysis illustrate the implications of effective thermal conductivity on temperature sensing zones on dies, and the significant impact of stack power density on overall operating temperature.

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“…Despite of being very accurate for thermal analysis, numerical methods like fine grain layoutlevel solution, presented in [1], and finite element modeling (FEM), used in [2], are inherently time consuming methods thus not suitable for system-level thermal simulations. In the other hand, the use of compact thermal models (CTM) offers a good tradeoff between accuracy and computational efficiency for early design stage analysis [3] [4].…”

Section: Introductionmentioning

confidence: 99%

Thermal modeling methodology for efficient system-level thermal analysis

Santos

Vivet

Matter³

et al. 2014

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference

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Heat dissipation is assumed to be one of the major challenges in the promising 3D integration technology. Very fine grain structures like TSVs and µ-bumps have considerable impact on heat dissipation properties. However, properly considering individual details of multi-length scale systems is still a challenge for efficient system-level thermal analysis. This paper presents a compact thermal modeling approach targeting fast steady-state and transient thermal analysis. The proposed method associates material homogenization and formal reduction techniques for model simplification, enabling to concurrently handle fine grain structures and constraints from board and package modeling. As a result, a dynamic compact thermal model is achieved offering system-level exploration capabilities. Simulation results of a complete system including a packaged 65nm memory-on-logic 3D circuit, socket and board show the thermal model is able to capture hotspot effects with fast simulation times. Comparisons with temperature measurements on the fabricated circuit demonstrate that accurate system-level thermal model of multi-length scale systems is feasible, showing an average error of 3.96% for steady-state temperature. Secondly, this paper reports an investigation study to show the thermal impact of TSV arrays, vertical stacking and die thickness, showing that 3D integration technology parameters considerably impacts silicon temperature and therefore should be properly modeled for accurate thermal analysis.

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Numerical and experimental characterization of the thermal behavior of a packaged DRAM-on-logic stack

Cited by 24 publications

References 20 publications

Thermal performance of 3D ICs: Analysis and alternatives

Thermal performance of 3D ICs: Analysis and alternatives

Physical characterization of steady-state temperature profiles in three-dimensional integrated circuits

Thermal modeling methodology for efficient system-level thermal analysis

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