Numerical Function Generators Using LUT Cascades

Sasao, Tsutomu; Nagayama, Shinobu; Butler, Jon T.

doi:10.1109/tc.2007.1033

Cited by 56 publications

(40 citation statements)

References 35 publications

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“…3 from the EVMDD. Since our NFG directly realizes the function table, it is more accurate than existing NFGs using polynomial approximation [7], [16], [25], [30], [31].…”

Section: Design Methods For Nfgs Using Evmddsmentioning

confidence: 99%

A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams

Nagayama

Sasao

Butler

2010

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper proposes a high-speed architecture to realize two-variable numeric functions. It represents the given function as an edgevalued multiple-valued decision diagram (EVMDD), and shows a systematic design method based on the EVMDD. To achieve a design, we characterize a numeric function f by the values of l and p for which f is an l-restricted Mp-monotone increasing function. Here, l is a measure of subfunctions of f and p is a measure of the rate at which f increases with an increase in the dependent variable. For the special case of an EVMDD, the EVBDD, we show an upper bound on the number of nodes needed to realize an l-restricted Mp-monotone increasing function. Experimental results show that all of the two-variable numeric functions considered in this paper can be converted into an l-restricted Mp-monotone increasing function with p = 1 or 3. Thus, they can be compactly realized by EVBDDs. Since EVMDDs have shorter paths and smaller memory size than EVBDDs, EVMDDs can produce fast and compact NFGs. key words: two-variable numeric function generators (NFGs), edgevalued multiple-valued decision diagrams (EVMDDs), edge-valued binary decision diagrams (EVBDDs), graph-based representation of numeric functions, programmable memory-based architecture

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“…3 from the EVMDD. Since our NFG directly realizes the function table, it is more accurate than existing NFGs using polynomial approximation [7], [16], [25], [30], [31].…”

Section: Design Methods For Nfgs Using Evmddsmentioning

confidence: 99%

A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams

Nagayama

Sasao

Butler

2010

IEICE Trans. Inf. & Syst.

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“…Thus, for numerically intensive or real-time applications, hardware accelerators, called numeric function generators (NFGs), are often required. The computation of numeric functions has been studied for more than 150 years [21], and various NFGs have been proposed [2], [4], [13], [16], [17]. Many existing NFGs are based on polynomial approximations.…”

Section: Introductionmentioning

confidence: 99%

Numeric Function Generators Using Piecewise Arithmetic Expressions

Nagayama

Sasao

Butler

2011

2011 41st IEEE International Symposium on Multiple-Valued Logic

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Abstract-This paper proposes new architectures for numeric function generators (NFGs) using piecewise arithmetic expressions. The proposed architectures are programmable, and they realize a wide range of numeric functions. To design an NFG for a given function, we partition the domain of the function into uniform segments, and transform a subfunction in each segment into an arithmetic spectrum. From this arithmetic spectrum, we derive an arithmetic expression, and realize the arithmetic expression with hardware. Since the arithmetic spectrum has many zero coefficients and repeated coefficients, by storing only distinct nonzero coefficients in a

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“…There is the function-specific design approach. For example, the CORDIC algorithms [1][2][3] for trigonometric and hyperbolic functions can be implemented in FPGA very efficiently and economically using fixed-point (FXP) data representation and arithmetic. For other functions, or the same set of functions in floating-point (FLP) data representation and arithmetic, one may use the direct look-up table (LUT) approach, in which function values are pre-calculated at certain sample points and stored in memory.…”

Section: Introductionmentioning

confidence: 99%

Automated optimization of look-up table implementation for function evaluation on FPGAs

Deng

Chakrabarti

Pitsianis

et al. 2009

Mathematics for Signal and Information Processing

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This paper presents a systematic approach for automatic generation of look-up-table (LUT) for function evaluations and minimization in hardware resource on field programmable gate arrays (FPGAs). The class of functions supported by this approach includes sine, cosine, exponentials, Gaussians, the central B-splines, and certain cylinder functions that are frequently used in applications for signal and image processing and data processing. In order to meet customer requirements in accuracy and speed as well as constraints on the use of area and on-chip memory, the function evaluation is based on numerical approximation with Taylor polynomials. Customized data precisions are supported in both fixed point and floating point representations. The optimization procedure involves a search in three-dimensional design space of data precision, sampling density and approximation degree. It utilizes both model-based estimates and gradient-based information gathered during the search. The approach was tested with actual synthesis results on the Xilinx Virtex-2Pro FPGA platform.

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Numerical Function Generators Using LUT Cascades

Cited by 56 publications

References 35 publications

A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams

A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams

Numeric Function Generators Using Piecewise Arithmetic Expressions

Automated optimization of look-up table implementation for function evaluation on FPGAs

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