Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state

Dehzangi, Arash; Larki, Farhad; Hutagalung, Sabar D.; Saion, Elias; Abdullah, Ahmad Makarimi; Hamidon, Mohd Nizar; Majlis, Burhanuddin Yeop; Kakooei, Saeid; Navaseri, Manizheh; Kharazmi, Alireza

doi:10.1049/mnl.2012.0590

Cited by 12 publications

(7 citation statements)

References 19 publications

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“…The coating layer also enhances the laser reflectivity of the cantilever. In fact, Cr/Pt and Au coated probe showed the acceptable result [33][34], but the Al reflex coating did not provide any acceptable results. Another issue is the order of oxidation.…”

Section: Methodsmentioning

confidence: 90%

Fabrication of p-Type Double Gate and Single Gate Junctionless Silicon Nanowire Transistor by Atomic Force Microscopy Nanolithography

Dehzangi

Larki

Hassan

et al. 2013

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In this work, we have investigated the fabrication of Double gate and Single gate Junctionless silicon nanowire transistor using silicon nanowire patterned on lightly doped (105 cm-3) p-type Silicon on insulator wafer fabricated by Atomic force microscopy nanolithography technique. Local anodic oxidation followed by two wet etching steps, Potassium hydroxide etching for Silicon removal and Hydrofluoric acid etching for oxide removal, were implemented to reach the structures. Writing speed and applied tip voltage were held in 0.6 µm/s and 8 volt respectively for Cr/Pt tip. Scan speed was held in 1.0 µm/s. The etching processes were elaborately performed and optimized by 30%wt. Potassium hydroxide + 10%vol. Isopropyl alcohol in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied. Negative gate voltage was unable to make significant effect on drain current to drive the device into accumulation mode.

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Section: Methodsmentioning

confidence: 90%

Fabrication of p-Type Double Gate and Single Gate Junctionless Silicon Nanowire Transistor by Atomic Force Microscopy Nanolithography

Dehzangi

Larki

Hassan

et al. 2013

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“…Low doping concentration is implemented in this work to control the scattering effect in the channel and avoid using high-cost material which usually is associated with the high-doped silicon technology. The operation of the device towards pinch off (Sorée et al , 2010) was previously investigated in the study by Dehzangi et al (2012). In this paper, we investigate the performance of SGJLT in the accumulation region.…”

Section: Introductionmentioning

confidence: 99%

Study of the side gate junctionless transistor in accumulation region

Dehzangi

Larki

Ali

et al. 2016

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Purpose The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition. Design/methodology/approach The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation. Findings We have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime. Originality/value The proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

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“…Recently, the researchers of the present study have reported the fabrication and experimental characterization of low doped p-type junctionless transistors with single and double lateral gate(s) through the unconventional method of atomic force microscopy (AFM) nanolithography [15] , [16] , [17] . Simulations of carrier's transport and pinch off mechanism of the device have been presented in Refs.…”

Section: Introductionmentioning

confidence: 99%

Effect of Geometric Parameters on the Performance of P-Type Junctionless Lateral Gate Transistors

et al. 2014

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This paper examines the impact of two important geometrical parameters, namely the thickness and source/drain extensions on the performance of low doped p-type double lateral gate junctionless transistors (DGJLTs). The three dimensional Technology Computer-Aided Design simulation is implemented to calculate the characteristics of the devices with different thickness and source/drain extension and based on that, the parameters such as threshold voltage, transconductance and resistance in saturation region are analyzed. In addition, simulation results provide a physical explanation for the variation of device characteristics given by the variation of geometric parameters, mainly based on investigation of the electric field components and the carries density variation. It is shown that, the variation of the carrier density is the main factor which affects the characteristics of the device when the device's thickness is varied. However, the electric field is mainly responsible for variation of the characteristics when the source/drain extension is changed.

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Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state

Cited by 12 publications

References 19 publications

Fabrication of p-Type Double Gate and Single Gate Junctionless Silicon Nanowire Transistor by Atomic Force Microscopy Nanolithography

Fabrication of p-Type Double Gate and Single Gate Junctionless Silicon Nanowire Transistor by Atomic Force Microscopy Nanolithography

Study of the side gate junctionless transistor in accumulation region

Effect of Geometric Parameters on the Performance of P-Type Junctionless Lateral Gate Transistors

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