Numerical Simulation Analysis of Switching Characteristics in the Source-Trench MOSFET’s

Abstract

In this paper, we compare the static and switching characteristics of the 4H-SiC conventional UMOSFET (C-UMOSFET), double trench MOSFET (DT-MOSFET) and source trench MOSFET (ST-MOSFET) through TCAD simulation. In particular, the effect of the trenched source region and the gate trench bottom P+ shielding region on the capacitance is analyzed, and the dynamic characteristics of the three structures are compared. The input capacitance is almost identical in all three structures. On the other hand, the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is reduced by 44% and 24%, respectively, compared to C-UMOSFET. Since the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is superior to that of C-UMOSFET, it improves high frequency figure of merit (HF-FOM: RON-SP × QGD). The HF-FOM of DT-MOSFET and ST-MOSFET is 289 mΩ∙nC, 224 mΩ∙nC, respectively, which is improved by 26% and 42% compared to C-UMOSFET. The switching speed of DT-MOSFET and ST-MOSFET are maintained at the same level as the C-UMOSFET. The switching energy loss and power loss of the DT-MOSFET and ST-MOSFET are slightly improved compared to C-UMOSFET.

4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

“…Figure 1 shows a cross-sectional schematic diagram of (a) Con-DTMOS [5], (b) SG-DTMOS, and (c) SHG-DTMOS. All the devices have a double trench structure, with a current spread layer (CSL) region that helps the current spread well [20].…”

“…Trench MOSFETs are one of the preferred device structures because of their low specific on-resistance (R on-sp ); however, a high electric field on the gate oxide and a large gatedrain capacitance (C rss ) degrade the breakdown voltage characteristics and the switching performance. To alleviate this problem, a double trench MOSFET (DTMOS) with a P + shielding region structure has been developed [3][4][5]. The double trench structure with a P + shielding region distributes the high electric field of the gate oxide to P + type doping on the source and gate regions.…”

High performance 4H-SiC MOSFET with deep source trench

“…The reliability issue of the gate oxide can be addressed by using a gate trench bottom P+ shielding region (BPR) structure [13][14][15]. The grounded BPR connected to the source protects the gate oxide from high voltage [16]. Furthermore, Rohm's double-trench MOSFETs (DT-MOSFETs), which were commercialized as a 1.2 kVclass [17], have the source region additionally trenched in the structure.…”

“…Therefore, we propose a deep source trench MOSFET (DST-MOSFET) in this study, which is a modified source trench MOSFET (ST-MOSFET) [16,19]. The DST-MOSFET forms a P-pillar through P+ doping in the ST region, which creates a superjunction (SJ) in the off state.…”

A Novel 4H-SiC Double Trench MOSFET with Built-In MOS Channel Diode for Improved Switching Performance

“…The DPT used for the switching simulation is shown in Figure8c, and the L C value was set to 60 µH. The switching-on time (T on ) was calculated as the total time required for V GS to reach from 10% of V IN to 90% of V DD (T d-on ), and the time required for V DS to reach from 90 to 10% of V DD (T r )[45]. The switching-off time (T off ) was also calculated as the total time required for V GS to reach from 90% of V IN to 10% of V DD (T d-off ), and the time required for V DS to reach from 10 to 90% of V DD (T f ).…”