Numerical simulation of electrical characteristics in nanoscale Si/GaAs MOSFETs

Li, Yiming; Chen, Wei‐Hsin

doi:10.1007/s10825-006-8854-x

Cited by 5 publications

(3 citation statements)

References 17 publications

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“…In a similar fashion, GaAs:Ge H-JLTFET could be fabricated through epitaxial growth with vertical interface. Reference [22] elaborates MBE growth of GaAs on Si and [23] shows the simulation results of nanoscale Si:GaAs MOSFETs and [24] explains epitaxial growth of GaAs on Si. InAs:Si interface, because of good bandgap and ease of fabrication [16], [25]- [27], is a point of attention due to its excellent characteristics.…”

Section: A Device Structurementioning

confidence: 99%

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

Asthana

Ghosh

Goswami

et al. 2014

IEEE Trans. Electron Devices

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Tunnel field-effect transistor (TFET) devices are gaining attention because of good scalability and they have very low leakage current. However, they suffer from low ON-current and high threshold voltage. In this paper, we present III-V heterojunctionless TFET (H-JLTFET) for circuit applications. This paper elaborates on interfacing of III-V with group IV semiconductors for heterojunction. Implementing heterojunction and bandgap engineering, we found that devices have significantly improved performance with very high speed even at very low operating voltage. As there is no doping junction present, future scaling could be feasible along with much higher speed of charge carriers than in silicon. GaAs:Si, Si:Si 0.3 Ge 0.7 , Si:InAs, and GaAs:Ge, H-JLTFET interface for 20-nm gate length (EOT = 2 nm) and dielectric, HfO 2 at V GS = 1 V and temperature of 300 K have I ON of 0.02-12.5 mA/µm, I ON /I OFF of 10 5 − 10 12 , and subthreshold swing (average) of 16-74 mV/decade. Index Terms-Gallium arsenide, hetero junctionless tunnel field-effect transistor (H-JLTFET), high-speed devices, indium arsenide, junctionless tunnel field-effect transistor (JLTFET), tunnel field-effect transistor (TFET).

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Section: A Device Structurementioning

confidence: 99%

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

Asthana

Ghosh

Goswami

et al. 2014

IEEE Trans. Electron Devices

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“…However, the leakage current will be increased at the same time. Consequently, proper channel capping or barrier layers [8][9][10][11] will be beneficial for device applications. However, the effect of channel capping layers on electircal and physical characteristics of the aforementioned devices has not been clearly investigated.…”

Section: Introductionmentioning

confidence: 99%

Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1−xGaxAs channel capping layer

Huang

2015

AIP Advances

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In this work, we study characteristics of 14-nm-gate InGaAs-based trigate MOSFET (metal-oxide-semiconductor field effect transistor) devices with a channel capping layer. The impacts of thickness and gallium (Ga) concentration of the channel capping layer on the device characteristic are firstly simulated and optimized by using three-dimensional quantum-mechanically corrected device simulation. Devices with In1−xGaxAs/In0.53Ga0.47As channels have the large driving current owing to small energy band gap and low alloy scattering at the channel surface. By simultaneously considering various physical and switching properties, a 4-nm-thick In0.68Ga0.32As channel capping layer can be adopted for advanced applications. Under the optimized channel parameters, we further examine the effects of channel fin angle and the work-function fluctuation (WKF) resulting from nano-sized metal grains of NiSi gate on the characteristic degradation and variability. To maintain the device characteristics and achieve the minimal variation induced by WKF, the physical findings of this study indicate a critical channel fin angle of 85o is needed for the device with an averaged grain size of NiSi below 4x4 nm2.

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“…III-V transistors with high electron mobility will increase the drive current, but the leakage current will also increase. Consequently, proper channel capping layers [9][10][11] will benefit device applications. III-V devices with vertical channel and capping layer will be an interesting study.…”

Section: Introductionmentioning

confidence: 99%

Impact of In<sub>1-x</sub>Ga<sub>x</sub>As Capping Layer on Characteristic of III-V Trigate MOSFET Devices

Huang

2014

Extended Abstracts of the 2014 International Conference on Solid State Devices and Materials

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In this work, we study the impact of channel capping layer on III-V trigate MOSFET. 3D device simulation shows that the 14nm device with In 1-x Ga x As/In 0.53 Ga 0.47 As channel has large driving current owing to small band gap and low alloy scattering at the channel surface. The mole fraction (x) of Ga, varying from 0.27 to 0.42, and the thickness of capping layer In 1-x Ga x As, ranging from 3 to 5 nm, are studied for device DC characteristic. The device with a 4-nm-thick In 0.68 Ga 0.32 As capping layer is promising for advanced device applications.

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Numerical simulation of electrical characteristics in nanoscale Si/GaAs MOSFETs

Cited by 5 publications

References 17 publications

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

Simulation study of 14-nm-gate III-V trigate field effect transistor devices with In1−xGaxAs channel capping layer

Impact of In<sub>1-x</sub>Ga<sub>x</sub>As Capping Layer on Characteristic of III-V Trigate MOSFET Devices

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