Numerical simulation of silicon wafer warpage due to thin film residual stresses

Abdelnaby, Ahmed; Potirniche, G. P.; Barlow, F.; Elshabini, Aicha; Groothuis, S.; Parker, R.

doi:10.1109/wmed.2013.6544506

Cited by 22 publications

(8 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To quantify and control the wafer shape, two global wafer shape metrics, that is, bow and warp, have been widely used 27 . Particularly, since the wafer warpage also translates into die warpage that has a detrimental impact on device performance, reliability, and even linewidth control in various processing steps, control of wafer curvature and flatness variations is one of the most important challenges in the fabrication of many electronic devices 84,85 . Wafer warpage can be defined as the height difference between the highest and the lowest points as depicted in Figure 1 86…”

Section: Related Literaturementioning

confidence: 99%

“…27 Particularly, since the wafer warpage also translates into die warpage that has a detrimental impact on device performance, reliability, and even linewidth control in various processing steps, control of wafer curvature and flatness variations is one of the most important challenges in the fabrication of many electronic devices. 84,85 Wafer warpage can be defined as the height difference between the highest and the lowest points as depicted in Figure 1. 86 Since wafer warpage is one of the main root causes leading to chip failures, early fault detection of wafer warpage and identification of the relationship between wafer warpage and die failures can enhance the semiconductor yield and minimize cost.…”

Section: Semiconductor Wafer Warpage Analysismentioning

confidence: 99%

See 1 more Smart Citation

A novel hybrid resampling for semiconductor wafer defect bin classification

Park

Pan

Montgomery

2022

Quality & Reliability Eng

View full text Add to dashboard Cite

Generally, defective dies on semiconductor wafer maps tend to form spatial clusters in distinguishable patterns which contain crucial information on specific problems of equipment or process, thus it is highly important to identify and classify diverse defect patterns accurately. However, in practice, there exists a serious class imbalance problem, that is, the number of the defective dies on semiconductor wafer maps is usually much smaller than that of the non-defective dies. In various machine learning applications, a typical classification algorithm is, however, developed under the assumption that the number of instances for each class is nearly balanced. If the conventional classification algorithm is applied to a class imbalanced dataset, it may lead to incorrect classification results and degrade the reliability of the classification algorithm. In this research, we consider the semiconductor wafer defect bin data combined with wafer warpage information and propose a new hybrid resampling algorithm to improve performance of classifiers. From the experimental analysis, we show that the proposed algorithm provides better classification performance compared to other data preprocessing methods regardless of classification models.

show abstract

Section: Related Literaturementioning

confidence: 99%

Section: Semiconductor Wafer Warpage Analysismentioning

confidence: 99%

A novel hybrid resampling for semiconductor wafer defect bin classification

Park

Pan

Montgomery

2022

Quality & Reliability Eng

View full text Add to dashboard Cite

show abstract

“…The development of electronic components is based on strict requirements to reduce their weight and size (Abdelnaby et al , 2013). Electronic components manufactured from ultrathin wafers are currently considered a promising solution for increasing integration while reducing size.…”

Section: Introductionmentioning

confidence: 99%

Reduction of the warping of a silicon wafer coated with two thin layers by minimal geometric modifications

Fatmi

Belhenini

Tougui

2023

View full text Add to dashboard Cite

Purpose The aim of this study is to make a contribution towards reducing the deflections of silicon wafers. The deformation of silicon wafers used in the manufacture of electronic micro-components is one of the most common problems encountered by industrialists during manufacturing. Stack warping is typically produced during the process of depositing thin layers on a substrate. This is due to the thermal-mechanical stresses caused by the difference between the thermal expansion coefficients of the materials. Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models. The results obtained are encouraging and clearly show a considerable reduction in wafer deformation. Design/methodology/approach Reducing wafer deformation is essential to increase reliability and improve quality. In this paper, the authors propose an approach based on minimal geometrical modifications to reduce the deformation of a silicon wafer coated with two thin layers. Numerical finite element models have been developed to evaluate the impact of geometrical modifications on warping amplitude. Finite element models have been validated compared with experimental models. Findings The results obtained are encouraging and clearly show a considerable reduction in wafer deformation. Originality/value This paper describes the influence of geometric modification on wafer deformation. The work show also the cruciality of stress reduction in the purpose to obtain less wafer deformation.

show abstract

“…There are several methods to measure the wafer curvature: the main ones exploit optical methods, but other approaches has been followed, see Chapter 14 in [ 15 ] or e.g., [ 16 , 17 ]. Numerical simulation is also pursued, to understand the influence of the materials and of the layer geometrical dimensions [ 18 ].…”

Section: Introductionmentioning

confidence: 99%

A New Approach for the Control and Reduction of Warpage and Residual Stresses in Bonded Wafer

et al. 2021

View full text Add to dashboard Cite

A geometrical modification on silicon wafers before the bonding process, aimed to decrease (1) the residual stress caused by glass frit bonding, is proposed. Finite element modeling showed that (2) by introducing this modification, the wafer out-of-plane deflection was decreased by 34%. Moreover, (3) fabricated wafers with the proposed geometrical feature demonstrated an improvement for the (4) warpage with respect to the plain wafers. A benefit for curvature variation and overall shape of the (5) bonded wafers was also observed.

show abstract

Numerical simulation of silicon wafer warpage due to thin film residual stresses

Cited by 22 publications

References 7 publications

A novel hybrid resampling for semiconductor wafer defect bin classification

A novel hybrid resampling for semiconductor wafer defect bin classification

Reduction of the warping of a silicon wafer coated with two thin layers by minimal geometric modifications

A New Approach for the Control and Reduction of Warpage and Residual Stresses in Bonded Wafer

Contact Info

Product

Resources

About