Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging

Abstract

Abstract-Layout camouflaging (LC) is a promising technique to protect chip design intellectual property (IP) from reverse engineers. Most prior art, however, cannot leverage the full potential of LC due to excessive overheads and/or their limited scope on an FEOL-centric and accordingly customized manufacturing process. If at all, most existing techniques can be reasonably applied only to selected parts of a chipwe argue that such "small-scale or custom camouflaging" will eventually be circumvented, irrespective of the underlying technique.In this work, we propose a novel LC scheme which is low-cost and generic-full-chip LC can finally be realized without any reservation. Our scheme is based on obfuscating the interconnects (BEOL); it can be readily applied to any design without modifications in the device layer (FEOL). Applied with split manufacturing in conjunction, our approach is the first in the literature to cope with both the FEOL fab and the enduser being untrustworthy. We implement and evaluate our primitives at the (DRC-clean) layout level; our scheme incurs significantly lower cost than most of the previous works. When comparing fully camouflaged to original layouts (i.e., for 100% LC), we observe on average power, performance, and area overheads of 12%, 30%, and 48%, respectively.Here we also show empirically that most existing LC techniques (as well as ours) can only provide proper resilience against powerful SAT attacks once at least 50% of the layout is camouflaged-only large-scale LC is practically secure. As indicated, our approach can deliver even 100% LC at acceptable cost. Finally, we also make our flow publicly available, enabling the community to protect their sensitive designs.

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

“…We assessed all flavors when applied at large scales for various benchmarks by 1) their APD cost, while taking our scheme end-to-end and evaluating GDSII layouts, and 2) their resilience against SATbased attacks while running the seminal attack [15], [31]. The exploratory study is detailed in [1]; we summarize it next.…”

“…In short, we select the flavor exemplified in Fig. 4 for the remainder of our study, as we found empirically that it offers the best security-cost trade-off [1].…”

“…E NSURING the integrity, security, and trustworthiness of integrated circuits (ICs) have become major concerns in recent years [2], [3]. One important aspect here is that the intellectual property (IP) of modern ICs can be duplicated without consent, resulting in financial losses for IP vendors, which This work is an extension of [1]. This work was supported in part by the Army Research Office under Grant 65513-CS, the Center for Cyber Security (CCS) at NYU/NYU AD, and the NYU AD Research Enhancement Fund (REF) under Grant RE218.…”

“…In other words, when facing camouflaged ICs, an attacker shall be rendered unable to infer the chip IP directly, as the IP is hidden within an obfuscated physical design. 1 Camouflaging is implemented traditionally at the device layer, e.g., by "look-alike" or ambiguous gates [6], [7], by secretly configured multiplexers [8], [9], or by the thresholddependent configuration of gates [10]- [12]. We note that prior art requires a fully trustworthy fabrication process, as the device obfuscation has to be realized by the foundry.…”

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects

“…See also Sec. 4.1. distinguishable traits of standard cells, e.g., using look-alike gates [24] or secretly configured MUXes [25], (ii) selective doping implantation for threshold-voltage-based obfuscation [26], [27], or (iii) rendering the BEOL wires and/or vias resilient against RE [28]. It is important to note that most schemes require alterations to the FEOL process, which can be complex and costly.…”