OBIG: the Architecture of an Output Buffered Switch with Input Groups for Large Switches

Olesinski, W.; Eberle, Hans; Gura, Nils

doi:10.1109/glocom.2007.46

Cited by 6 publications

(8 citation statements)

References 10 publications

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“…The architecture we consider here is very close to that described by Olesinski et al in [1] for OBIG switches. Consider an N × N switch with N input ports and N output ports, physically distributed across M chips.…”

Section: Switch Model and The Scheduling Problemmentioning

confidence: 87%

“…Recently, a single stage, distributed switch architecture, OBIG (output buffers with input groups) was proposed in [1] and leveraged for enabling a switch with 256 ports and an aggregate bandwidth of 2.5 Tbps. An OBIG switch is distributed over multiple chips which communicate via high speed interconnects called proximity communication (PC) links 1 .…”

Section: Introductionmentioning

confidence: 99%

“…An OBIG switch is distributed over multiple chips which communicate via high speed interconnects called proximity communication (PC) links 1 . Each chip is equipped with internal buffers at strategically chosen crosspoints, as described in Section II.…”

Section: Introductionmentioning

confidence: 99%

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Backlog Aware Scheduling for Large Buffered Crossbar Switches

Dua

Yolken

Bambos

et al. 2008

2008 IEEE International Conference on Communications

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A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with input groups), distributes the switch fabric across multiple chips, which communicate via high speed interconnects enabled by proximity communication (PC), a recently developed circuit technology [2]. An OBIG switch aggregates multiple input flows inside the switch fabric, thereby significantly reducing the amount of memory required for internal buffers, vis-à-vis a conventional buffered crossbar, which has buffers at every crosspoint. Thus, the OBIG architecture is promising for realizing terabit switches with hundreds of ports. This paper studies packet scheduling algorithms which help realize the potential of OBIG-like switch architectures. The emphasis here is on designing backlog aware scheduling algorithms, while ensuring desirable traits such as low computational complexity and scalability. The efficacy of the proposed scheduling algorithms with respect to performance metrics such as average delay and fairness is demonstrated via simulations under a variety of scenarios.

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Section: Switch Model and The Scheduling Problemmentioning

confidence: 87%

Section: Introductionmentioning

confidence: 99%

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Backlog Aware Scheduling for Large Buffered Crossbar Switches

Dua

Yolken

Bambos

et al. 2008

2008 IEEE International Conference on Communications

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“…Specifically, we proposed an architecture called Output Buffered Switch with Input Groups (OBIG) [10] that exploits a novel chip interconnect technology called Proximity Communication (PxC) introduced in [2], [7]. We have shown how this architecture and technology can be used to build a 256-port, 2.5Tbps, single-stage switch [10], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

“…We have shown how this architecture and technology can be used to build a 256-port, 2.5Tbps, single-stage switch [10], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

Scalable Alternatives to Virtual Output Queuing

Olesinski

Eberle

Gura

2009

2009 IEEE International Conference on Communications

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To avoid head of line blocking in switches, Virtual Output Queues (VOQs) are commonly used. However, the number of VOQs grows quadratically with the number of ports, making this approach impractical for large switches. In this paper, we propose Dynamic Switch Buffer Management (DSBM) to tackle this problem. Similar to DBBM [3], it saves memory by reducing the number of buffers. Our scheme significantly improves the performance by dynamically assigning the incoming cells to the least occupied buffers.

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