Occam-pi as a High-Level Language for Coarse-Grained Reconfigurable Architectures

International Journal of Reconfigurable Computing

2012

Self Cite

Massively parallel reconfigurable architectures, which offer massive parallelism coupled with the capability of undergoing run-time reconfiguration, are gaining attention in order to meet the increased computational demands of high-performance embedded systems. We propose that the occam-pi language is used for programming of the category of massively parallel reconfigurable architectures. The salient properties of the occam-pi language are explicit concurrency with built-in mechanisms for interprocessor communication, provision for expressing dynamic parallelism, support for the expression of dynamic reconfigurations, and placement attributes. To evaluate the programming approach, a compiler framework was extended to support the language extensions in the occam-pi language and a backend was developed to target the Ambric array of processors. We present two case-studies; DCT implementation exploiting the reconfigurability feature of occam-pi and a significantly large autofocus criterion calculation based on the dynamic parallelism capability of the occam-pi language. The results of the implemented case studies suggest that the occam-pi-language-based approach simplifies the development of applications employing run-time reconfigurable devices without compromising the performance benefits.

“…We have also previously demonstrated the applicability of the approach on another reconfigurable architecture, namely, PACT XPP [5]. The contributions of this paper are as follows.…”

Section: International Journal Of Reconfigurable Computingmentioning

confidence: 99%

Occam-pi for Programming of Massively Parallel Reconfigurable Architectures

Ul-Abdin

International Journal of Reconfigurable Computing

2012

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“…In order to incorporate mobile semantics into the language, the keyword MOBILE has been introduced as a qualifier for data types [5]. The definition of the MOBILE types is consistent with the ordinary types when considered in the context of defining expressions, procedures and functions.…”

Section: B Language Extensions To Support Reconfigurabilitymentioning

confidence: 99%

“…The front end consists of phases up to machine independent optimization and the backend includes the remaining phases that are dependent upon the target machine architecture. The Ambric and the eXtreme Processing Platform (XPP) backends were developed in previous works [10] [5].…”

Section: Occam-pi Compilation To P2012mentioning

confidence: 99%

“…In earlier works, the frontend of the compiler has been extended to support mobile data and channel types, dynamic process invocation, and process placement attributes [10] [5].…”

Section: A Frontendmentioning

confidence: 99%

“…We have also previously demonstrated the applicability of the approach on a medium-grained reconfigurable architecture viz., PACT XPP [5]. This paper is focused on using occam-pi to map applications to an embedded manycore architecture, the Platform 2012 (P2012) [6] which is currently under joint development by STMicroelectronics and CEA.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Managing Dynamic Reconfiguration for Fault-tolerance on a Manycore Architecture

Ul-Abdin

Gebrewahid

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops &Amp; PhD Forum

2012

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Abstract-With the advent of manycore architectures comprising hundreds of processing elements, fault management has become a major challenge. We present an approach that uses the occam-pi language to manage the fault recovery mechanism on a new manycore architecture, the Platform 2012 (P2012). The approach is made possible by extending our previously developed compiler framework to compile occam-pi implementations to the P2012 architecture. We describe the techniques used to translate the salient features of the occam-pi language to the native programming model of the P2012 architecture. We demonstrate the applicability of the approach by an experimental case study, in which the DCT algorithm is implemented on a set of four processing elements. During runtime, some of the tasks are then relocated from assumed faulty processing elements to the faultless ones by means of dynamic reconfiguration of the hardware. The working of the demonstrator and the simulation results illustrate not only the feasibility of the approach but also how the use of higher-level abstractions simplifies the fault handling.

Programming Real-Time Image Processing for Manycores in a High-Level Language

Gebrewahid

Zain-ul-Abdin

Lecture Notes in Computer Science

et al. 2013

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Abstract. Manycore architectures are gaining attention as a means to meet the performance and power demands of high-performance embedded systems. However, their widespread adoption is sometimes constrained by the need for mastering proprietary programming languages that are low-level and hinder portability.We propose the use of the concurrent programming language occam-pi as a high-level language for programming an emerging class of manycore architectures. We show how to map occam-pi programs to the manycore architecture Platform 2012 (P2012). We describe the techniques used to translate the salient features of the language to the native programming model of the P2012. We present the results from a case study on a representative algorithm in the domain of real-time image processing: a complex algorithm for corner detection called Features from Accelerated Segment Test (FAST). Our results show that the occam-pi program is much shorter, is easier to adapt and has a competitive performance when compared to versions programmed in the native programming model of P2012 and in OpenCL. Keywords: Parallel programming; Occam-pi; Manycore architectures; Realtime image processing. IntroductionThe design of high-performance embedded systems for signal processing applications is facing the challenge of increased computational demands. Moore's Law still gives us more transistors per chip but, since increased processor clock speed is no longer an option, current hardware designs are shifting to manycore architectures to cope with the computational demand of DSP applications. However, developing applications that employ such architectures poses several other challenging tasks. The challenges include learning multiple proprietary low-level languages for describing the communication structure of the application and the computational kernels, as well as partitioning and decomposing the application into several sub-tasks that can execute concurrently. Sequential programming languages (like C, C++, Java …), which were originally designed for sequential computers with unified memory systems and rely