Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

Abstract

Abstract-In this work, we present Odin II, a framework for Verilog Hardware Description Language (HDL) synthesis that allows researchers to investigate approaches/improvements to different phases of HDL elaboration that have not been previously possible. Odin II's output can be fed into traditional back-end flows for both FPGAs and ASICs so that these improvements can be better quantified. Whereas the original Odin [1] provided an open source synthesis tool, Odin II's synthesis framework offers significant improvements such as a unified environment for both front-end parsing and netlist flattening. Odin II also interfaces directly with VPR [2], a common academic FPGA CAD flow, allowing an architectural description of a target FPGA as an input to enable identification and mapping of design features to custom features. Furthermore, Odin II can also read the netlists from downstream CAD stages into its netlist data-structure to facilitate analysis. Odin II can be used for a wide range of experiments; in this paper, we show three specific instances of how Odin II can be used by ASIC and FPGA researchers for more than basic synthesis. Odin II is open source and released under the MIT License.

Visualization support for FPGA architecture exploration

“…the design is changed, which allows one to apply changes very easily [15]. In comparison to other CAD flows, the internal data structure of Odin II is not focused on saving memory but on speeding up possible changes.…”

“…Odin II was introduced in [15]. It is "a framework for Verilog Hardware Description Language(HDL) synthesis", which is an improved version of…”

“…Two inputs are needed during the procedure. The first one is the Verilog HDL design, which is parsed to create an "abstract syntax tree [15]. The second is the FPGA architecture description.…”

“…Some of them are: Icarus [12], Veriwell [13] and FreeHDL [14], "which mainly concentrate on simulation and analysis of digital designs [15]." The advantages of such an application is, that no resources are needed Comparison [16] in addition to the actual computation, that computations can be performed automated on servers etc.…”

Three Dimensional FPGA Architecture with Fewer TSVs

“…Figure 8 shows the evaluation flow. We use the conventional FPGA CAD flow, performing elaboration with ODIN II [22], technology mapping with ABC, and placement with VTR 7.0. Routing and power estimation are executed using our developed tools, EasyRouter and EasyPower.…”