Off-state breakdown walkout in high-power PHEMT's

Abstract

Conventional wisdom suggests that in pseudomor-phic high electron mobility transistors (pHEMT's), the field between the drain and the gate determines off-state breakdown, and that the drain to gate voltage therefore sets the breakdown voltage of the device. Thus, the two terminal breakdown voltage is a widely used figure of merit, and most models for breakdown focus on the depletion region in the gate-drain gap, while altogether ignoring the source. We present extensive new measurements and simulations that demonstrate that for power pHEMT's, the electrostatic interaction of the source seriously degrades the device's gate-drain breakdown. We identify the key aspect ratio that controls the effect, L L LG G G : x x xD D D, where L L LG G G is the gate length and x x xD D D is the depletion region length on the drain. This work establishes that the design of the source must be taken into consideration in the engineering of high-power pHEMT's. Index Terms-Breakdown voltage, electric breakdown, electron tunneling, power HEMT's power MODFET's.

Hot electron degradation of the DC and RF characteristics of AlGaAs/InGaAs/GaAs PHEMT's

“…The answer lies in the presence of some "breakdown walkout" during our stress experiment, as demonstrated by the decrease (not shown here), with increasing stress time, of both the drain and gate current measured at the stress bias point V, V). This phenomenon was observed on different PHEMT samples [12], [15], and is thought to be due to electron trapping at the surface of the gate-drain access region giving rise to a decrease of the peak electric field in the channel; this reduces the impact ionization rate, therefore and decrease. So, due to "breakdown walkout" both the mechanisms that we have indicated above as possible reasons for the storage of positive charge in deep traps under the gate, namely the electric field and the gate current, decrease with time during our stress, until a condition is reached where hole release becomes dominant, and recovery begins.…”

“…These effects were generally attributed to trap creation and/or charge accumulation under the gate or at the interface between semiconductor and passivation in the gatedrain region. Off-state, high drain-gate bias stress experiments were carried out as well [15], [16] However, as far as the rf effects of such stress conditions are concerned, very limited data are available in the literature. The published works generally focused on high power devices, therefore no indication was given on the possible effects of the stress on the PHEMT small-signal parameters.…”

Hot electron effects and degradation of GaAs and InP HEMTs for microwave and millimetre-wave applications

“…The reduction of the surface potential smears out the longitudinal electric field profile between gate and drain, lowers the field peak and consequently hinders electron heating and impact ionization (an effect first observed in GaAs MESFETs [32]), which are responsible for three-terminal breakdown; the HE electroluminescence intensity is reduced likewise [33]. Consistently with this theory, off-state stress experiments performed on power PHEMTs [34] showed a marked dependence of the walk out effect on the wafer surface conditions prior to PECVD-SiN deposition, and on the features of the passivation process (see for instance [35] for a comparison between SiO and SiN MESFET passivation from the standpoint of surface state density and gate-drain breakdown); the lowfrequency gate noise voltage spectral density also decreased in correspondence with the walk out [36,37].…”

Hot carrier reliability in high-power PHEMTs

“…The devices used for this study are described elsewhere [8]. The test devices were mounted in a dual-in-line package(D1P).…”

“…generated from the impact ionization process[8]. Thus, the devices biased at the normal operation condition in power 46 -GaAs IC Symposium 0-7803-3504-X196 $5.00 0 1996 IEEE…”