Off-state degradation with ac bias in PMOSFET

Park, Segeun; Jung, Hoeryong; Oh, Jeong-Hoon; Kim, Ilgweon; Hong, Hye Jin; Jin, Gyoyoung; Roh, Yonghan

doi:10.1016/j.microrel.2016.08.007

Cited by 1 publication

(3 citation statements)

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“…As the distance between the DC and the gate becomes smaller and smaller, it is considered essential to check the immunity to hot electron-induced punchthrough (HEIP) reliability. This is even more important in DRAM operations, since there are PMOSFETs operating at a high voltage (VPP) as a part of the sub word line driver (SWD) [11]. For this, we applied an AC stress to the PMOSFET with the conditions VG = VB = VPP, VD = -0.3 V, and an AC pulse from 0 to VPP was forced on VS. To accelerate the tests, the time was fixed As the distance between the DC and the gate becomes smaller and smaller, it is considered essential to check the immunity to hot electron-induced punchthrough (HEIP) reliability.…”

Section: Resultsmentioning

confidence: 99%

“…For this, we applied an AC stress to the PMOSFET with the conditions VG = VB = VPP, VD = -0.3 V, and an AC pulse from 0 to VPP was forced on VS. To accelerate the tests, the time was fixed As the distance between the DC and the gate becomes smaller and smaller, it is considered essential to check the immunity to hot electron-induced punchthrough (HEIP) reliability. This is even more important in DRAM operations, since there are PMOSFETs operating at a high voltage (V PP ) as a part of the sub word line driver (SWD) [11]. For this, we applied an AC stress to the PMOSFET with the conditions V G = V B = V PP , V D = -0.3 V, and an AC pulse from 0 to V PP was forced on V S .…”

Section: Resultsmentioning

confidence: 99%

“…For this, we applied an AC stress to the PMOSFET with the conditions V G = V B = V PP , V D = -0.3 V, and an AC pulse from 0 to V PP was forced on V S . To accelerate the tests, the time was fixed to 50 s and the V PP was strengthened to 4-6 V. All the tests were conducted at room temperature, which is known to be the worst condition for electron trapping [11].…”

Section: Resultsmentioning

confidence: 99%

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The Performance Enhancement of PMOSFETs and Inverter Chains at Low Temperature and Low Voltage by Removing Plasma-Damaged Layers

et al. 2022

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In this work we report on the improvement in cold temperature characteristics of PMOSFETs and inverter circuits by removing the plasma-damaged layer of the source/drain contacts. We removed the plasma-induced damage on the Si using a simple in situ Si soft treatment technique. We found by transmission electron microscope (TEM) analysis that the damaged amorphous layer reduced from 52 Å to 42 Å and 35 Å with a treatment time of 10 and 20 s, respectively. As a result, the resistances of both the n+ and p+ contacts decreased for all contact sizes and the standard deviations at the cold temperature were suppressed by 45%. At −25 °C, the saturation current of the PMOSFET increased by 3% and the propagation delay time (tPD) decreased by 2%. The tPD increases by 19.3% when the temperature decreases from 85 °C to −25 °C, and the operating voltage decreases from 1.2 V to 0.95 V at the same time. However, this increase can be reduced to 17% by applying the soft treatment for 10 s. This simple and short time process will be considered essential for both mobile applications and automotive applications of dynamic random access memory (DRAM) devices requiring a low-voltage and low-temperature operation.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

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