Offset compensation in comparators with minimum input-referred supply noise

Wong, K.-L.J.; Yang, Chih-Kong Ken

doi:10.1109/jssc.2004.826317

Cited by 100 publications

(42 citation statements)

References 6 publications

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“…This lowers the trip-point voltage of the crosscoupled inverters, ensuring that they do not activate too early. Offset compensation is implemented as programmable currentsteering ( Figure 2b) and capacitive ( Figure 2c) DACs [9], for coarse-and fine-compensation, respectively. Figure 2h shows a diode-emulation circuit that is used to characterize the receiver's performance when decoupled from the optical devices.…”

Section: Receiver Architecturementioning

confidence: 99%

A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI

Georgas

Orcutt

Ram

et al. 2012

IEEE J. Solid-State Circuits

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Abstract-A monolithically-integrated optical receiver for lowenergy on-chip and off-chip communication is presented. The monolithic photodiode integration enables the energy-efficient and high-sensitivity sense-amplifier-based receiver design. The receiver is characterized in situ and shown to operate with μA-sensitivity at 3.5 Gb/s with a power consumption of 180 μW (52 fJ/bit) and area of 108 μm 2 . This work demonstrates that photonics and electronics can be jointly integrated in a standard 45-nm SOI process.

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Section: Receiver Architecturementioning

confidence: 99%

A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI

Georgas

Orcutt

Ram

et al. 2012

IEEE J. Solid-State Circuits

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“…If the total equivalent offset voltage of comparator has been modeled as V off on its input, the remained equivalent input referred offset voltage after offset cancellation is as below: 6 × V off (3) As above equation, the input referred offset voltage can be eliminated by zeroing the numerator term. This is accomplished by choosing appropriate regeneration switch (M sn and M sp ) size in comparison with the size of M5 and M6 transistors to minimize 2g sw +g out +g m15,16 −g m5, 6 term. The values of g out and g m5, 6 are not constant through temperature and process variations.…”

Section: Proposed Low Offset Track and Latch Comparatormentioning

confidence: 99%

“…This is accomplished by choosing appropriate regeneration switch (M sn and M sp ) size in comparison with the size of M5 and M6 transistors to minimize 2g sw +g out +g m15,16 −g m5, 6 term. The values of g out and g m5, 6 are not constant through temperature and process variations. Therefore the g sw is assumed adjustable conductance.…”

Section: Proposed Low Offset Track and Latch Comparatormentioning

confidence: 99%

“…This makes g m5, 6 be greater than (2g sw +g out +g m15,16 ) and oscillation will be started in replica comparator based Schmitt-trigger oscillator. If the oscillation be still with large amplitude (g m5, 6 is too greater than 2g sw +g out +g m15,16 ), the V BP voltage will be decreased to cause g sw increasing and finally the determined V BP value in oscillator feedback will still cause oscillation with small amplitude in Schmitt-trigger oscillator. The size of Msp transistor in main comparator circuit is considered something greater than its size in replica circuit.…”

Section: Proposed Low Offset Track and Latch Comparatormentioning

confidence: 99%

“…The size of Msp transistor in main comparator circuit is considered something greater than its size in replica circuit. This increases the value of g sw in main circuit and guarantees the (2g sw +g out +g m15,16 ) term be closely greater than g m5, 6 and makes the value of equation (2) be positive and high regardless of temperature and process variations.…”

Section: Proposed Low Offset Track and Latch Comparatormentioning

confidence: 99%

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An accurate track-and-latch comparator

Sadeghipour

2012

IEICE Electron. Express

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Abstract:In this paper, a new accurate track and latch comparator circuit is presented. The Offset voltage of latch is compensated by negative feedback loop and the low offset voltage is achieved without pre-amplifiers. The pull up devices in modified regeneration latch is turned off to reduce quiescent current of comparator within the tracking phase. The Monte-Carlo simulation results for the designed comparator in 0.18 µm CMOS process show that equivalent input referred offset voltage is 200 µV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 400 µW from a 1.8 V supply while operates in 500 MHz clock frequency. The power consumption improvement is up to 33% over previously reported structure.

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Fast adaptive comparator offset calibration in pipeline ADC with self‐repairing thermometer to binary encoder

Ginés

Peralías

Aledo

et al. 2019

Circuit Theory & Apps

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Summary This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15‐bit resolution (74 dB‐Signal‐to‐noise plus Distortion Ratio [SNDR]). A self‐repairing (SR) thermometer‐to‐binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one‐half least‐significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15‐bit pipeline ADC using a novel calibrated dynamic‐latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.

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Offset compensation in comparators with minimum input-referred supply noise

Cited by 100 publications

References 6 publications

A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI

A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI

An accurate track-and-latch comparator

Fast adaptive comparator offset calibration in pipeline ADC with self‐repairing thermometer to binary encoder

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