Ohmic Contacts on p‐GaN

Abstract

With the development of GaN-based optoelectronic devices, the need for p-GaN contacts with low resistivity, good thermal stability, and high transparency or refl ectivity has become more pressing. Various contact schemes to satisfy these requirements have been investigated in the past two decades. In this progress report, the main developments of contacts on p-GaN throughout these years are summarized. The primary focus is on the materials aspects of the contacts and the functional mechanisms related to their relevant properties.

AlGaN/GaN Superlattice‐Based p‐Type Field‐Effect Transistor with Tetramethylammonium Hydroxide Treatment

“…[18] Additionally, the high p-GaN work function at typical doping levels results in challenges to making ohmic contacts to p-type GaN. [19] In view of these challenges, III-nitride based p-FETs have received significantly less attention compared to GaN-based HEMTs. [14,[20][21][22][23][24][25][26][27] In this report, we present the first p-type GaN/AlGaN superlattice pFET.…”

An E-Mode p-Channel GaN MOSHFET for a CMOS Compatible PMIC

“…Accordingly, the maximum hole mobility is limited to [14] in a field dependent mobility model [23]. Additionally, a contact resistance of is used for source and drain contacts to p-GaN, which is an average contact resistance reported for p-GaN [24]. Charge and trap densities of and at oxide/GaN interface are found sufficient to match the experimental characteristics reported in [15].…”

Review of the Recent Progress on GaN-Based Vertical Power Schottky Barrier Diodes (SBDs)

“…A low activation ration of Mg + for GaN results in low hole concentration, which can affect the GaN crystal quality causing low mobility and carrier concentration. The poor activation of dopants (Mg + atoms) has only produced 10 15 -10 17 cm −3 orders of magnitude of the carrier concentration [21]. Besides, the extremely high temperatures required to activate the implanted Mg during the annealing process also damage the GaN surface [61,62].…”

“…The typical schematic structure of GaN SBD is shown in Figure 1a,b, including quasi-vertical and fully-vertical structure [16][17][18][19][20][21][22]. For the quasi-vertical GaN SBD, a mesa structure is processed and both Quasi-vertical SBDs have several drawbacks [20,22]: (1) nonuniform distribution of current, (2) the current crowding problems, (3) large total device area, and (4) the deep etched sidewall process.…”

“…However, a large number of dislocations in the GaN drift layer can cause leakage current when device is reverse biased [40,41]. To study the substrates impact on the performance of GaN-based power device, Figure 2 summarizes the data from The GaN epitaxy layer grown on GaN substrate has lower dislocation densities than foreign substrates (e.g., Si, sapphire, or SiC), because of low lattice mismatch and low thermal expansion coefficient mismatch [20][21][22][23][24][25][26][27]. However, the dislocation density of GaN-on-GaN is limited by the defect density in the GaN substrate [28][29][30].…”